Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-06-24
2000-05-02
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 23, 713100, 709 1, 709104, G06F 900
Patent
active
060584661
ABSTRACT:
A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.
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Chamdani Joseph I.
Panwar Ramesh
An Meng-Ai T.
El-Hady Nabil
Kubida William J.
Langley Stuart T.
Sun Microsystems Inc.
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