System for aligning bytes of variable multi-bytes length operand

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395375, 364DIG1, 3642393, 3642433, 3642451, 3642548, 3642549, 364259, 3642718, G06F 930

Patent

active

051685710

ABSTRACT:
A hardware data string operation controller is provided which (1) performs variable length main store string operation; (2) executes at least a subset of both left to right and right to left instructions, having variable length multibyte operands; and (3) performs multicycle storage to storage operations on variable length multibyte operand data, all under the control of a single control word. The controller comprises (a) means for dynamically determining (and if necessary, adjusting) the maximum number of operand related data string bytes that can be processed (by the controller) during each machine cycle (referred to as"data mode" calculation/alteration); (b) means for performing partial machine "holdoffs" (i.e., inhibiting selectively chosen register updates without stopping all processor operation), whenever at least a plurality of machine cycles is required to completely execute a control word; and (c) means for predicting storage operations (fetches and stores required by the controller) during the machine cycle prior to the cycle during which said storage operations are to be performed.

REFERENCES:
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patent: 4037213 (1977-07-01), Atkins et al.
patent: 4317170 (1982-02-01), Wada et al.
patent: 4456955 (1984-06-01), Yanagita et al.
patent: 4580238 (1986-04-01), Sawada
patent: 4654781 (1987-03-01), Schwartz et al.

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