System for accelerated graphics port address remapping interface

Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit

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345521, 711202, G06F 1206

Patent

active

060696389

ABSTRACT:
A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

REFERENCES:
patent: 4937734 (1990-06-01), Bechtolsheim
patent: 4969122 (1990-11-01), Jensen
patent: 5121487 (1992-06-01), Bechtolsheim
patent: 5133058 (1992-07-01), Jensen
patent: 5155816 (1992-10-01), Kohn
patent: 5222222 (1993-06-01), Mehring et al.
patent: 5263142 (1993-11-01), Watkins et al.
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5265227 (1993-11-01), Kohn et al.
patent: 5265236 (1993-11-01), Mehring et al.
patent: 5305444 (1994-04-01), Becker et al.
patent: 5313577 (1994-05-01), Meinerth et al.
patent: 5315696 (1994-05-01), Case et al.
patent: 5315698 (1994-05-01), Case et al.
patent: 5321806 (1994-06-01), Meinerth et al.
patent: 5321807 (1994-06-01), Mumford
patent: 5321810 (1994-06-01), Case et al.
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5361340 (1994-11-01), Kelly et al.
patent: 5392393 (1995-02-01), Deering
patent: 5396614 (1995-03-01), Khalidi et al.
patent: 5408605 (1995-04-01), Deering
patent: 5426750 (1995-06-01), Becker et al.
patent: 5440682 (1995-08-01), Deering
patent: 5446854 (1995-08-01), Khalidi et al.
patent: 5465337 (1995-11-01), Kong
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5491806 (1996-02-01), Horstmann et al.
patent: 5500948 (1996-03-01), Hinton et al.
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5546555 (1996-08-01), Horstmann et al.
patent: 5548739 (1996-08-01), Yung
patent: 5553023 (1996-09-01), Lau et al.
patent: 5584014 (1996-12-01), Nayfeh et al.
patent: 5586283 (1996-12-01), Lopez-Aguado et al.
patent: 5664161 (1997-09-01), Fukushima et al.
Accelerated Graphics Port Interface Specification. Revision 1.0. Intel Corporation. Jul. 31, 1996. 81 pgs.
LSI Logic L64852 Mbus-to-SBus Controler (M2S) Technical Manual. LSI Logic Corporation (1993). 73 pgs.

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