Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Patent
1997-06-25
2000-05-30
Chauhan, Ulka J.
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
345521, 711202, G06F 1206
Patent
active
060696389
ABSTRACT:
A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.
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Chauhan Ulka J.
Micron Electronics Inc.
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