System enabling high-speed convolution processing of image data

Details System enabling high-speed convolution processing of image data System enabling high-speed convolution processing of image data

1986-09-17

1990-03-06

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 15336

Patent

active

049071823

ABSTRACT:
A system enabling high-speed convolution processing of image data, which system includes at least one arithmetical unit having a number of identical processing cells interconnected in semisystolic formation and designed to perform one- or two-dimensional convolutions with separable variables; and a memory block designed to store at least the aforementioned data to be subjected to such convolution processing.

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Kung et al., "Hardware Pipelines for Multi-Dimensional Convolution and Resampling", Computer Architecture for Pattern Analysis and Database Management, Nov. 1981, pp. 273-278, IEEE Computer Society Press.
Blackmer et al., "A 200 MOPS Systolic Processor", SPIE Conference Proc., vol. 298, Real-Time Signal Processing IV, Aug. 1981, pp. 1-9.
Kung, "Systolic Algorithms for the CMU Ways Processor", Systolic Signal Processing Systems, 1987, Marcel Decker, pp. 570-577.
Kung, "Why Systolic Architectures", IEEE Computer, vol. 15, #1, pp. 37-46, Jan. 1982.

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