System crash detect and automatic reset mechanism for processor

Details System crash detect and automatic reset mechanism for processor System crash detect and automatic reset mechanism for processor

1991-11-21

1994-07-26

Atkinson, Charles E.

Excavating

371 163, G06F 1114

Patent

active

053332857

ABSTRACT:
A hardware and software mechanism is provided for ensuring that a feature processor card, included with other feature cards in a host system, can be reset without interrupting software running on other feature cards. A delay is provided that starts counting each time a watchdog timer expires. If the watchdog timer is reset by an interrupt service routine, then the feature card processor is assumed to be reset. But, if the watchdog timer is not reset before the delay timer expires, then it is assumed that service routine is corrupt and that external reset of the feature card is required. Upon expiration of the watchdog, an error signal is sent, via the system bus, to the host CPU. Recovery code that is resident on the host CPU is then run and resets the CPU on the feature card. A reset signal is output from the host CPU, via the system bus, to a reset register on the feature card which then forwards the signal to the feature card CPU, thereby initiating reset of the system.

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IBM TDB "Software-Controlled Watchdog and Reboot Circuit Device for Personal Systems," vol. 31, No. 12, May 1989, pp. 374-375.
IBM TDB "Automatic Hardware Detection of Personal Computer Software System Resets and Re-Initial Program Load," Jan. 1989, pp. 162-164.

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