Patent
1996-01-30
1998-06-30
Butler, Dennis M.
395552, 395555, 395558, G06F 104
Patent
active
057746990
ABSTRACT:
In a controller which generates a clock to be output to a CPU on the basis of a fundamental clock, and incorporates control logic circuits such as DRAM control, CPU cycle control, and the like, the internal operation clock is switched to either an internally generated clock or a clock obtained by re-inputting a clock which is temporarily output to an external circuit. Only the clock to be output to the CPU can be delayed with respect to the clock used for generating a DRAM control signal, and the delay time of the DRAM control signal with respect to the CPU clock can be minimized.
REFERENCES:
patent: 4931986 (1990-06-01), Daniel et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5446867 (1995-08-01), Young et al.
Butler Dennis M.
Kabushiki Kaisha Toshiba
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