Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-16
2002-11-05
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S211000, C345S213000
Reexamination Certificate
active
06476789
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system construction of semiconductor devices, that has a plurality of the same semiconductor devices in a cascade connection, and further concerns a liquid crystal display device module using the system construction of the semiconductor devices.
BACKGROUND OF THE INVENTION
As shown in
FIG. 10
, a conventional liquid crystal display device module has a semiconductor device system, in which source driver LSI (large Scale Integrated Circuit) chips
51
and gate driver LSI chips
52
are respectively mounted on TCPs (Tape Carrier Package)
53
. Further, the output terminals of the source driver LSI chips
51
and the gate driver LSI chips
52
are subjected to a thermocompression bonding and are electrically connected to terminals (not shown) made of ITO (Indium Tin Oxide) on a liquid crystal panel
54
via, for example, an ACF (Anisotropic Conductive Film).
Also, the TCPs
53
are electrically connected with a flexible substrate
55
in the same manner as the output terminals of the source driver LSI chips
51
and the gate driver LSI chips
52
. With this arrangement, color image data signals (three kinds of signals, R·G·B) are supplied to the source driver LSI chips
51
, and control signals and source lines, etc. are supplied to the source driver LSI chips
51
or the gate driver LSI chips
52
, from a controller circuit
56
via lines disposed on the flexible substrate
55
.
Here, eight TCPs
53
have the source driver LSI chips
51
and serve as first through eighth source drivers. Namely, eight source driver LSI chips
51
of the same structure are cascaded. Additionally, in this arrangement, two gate driver LSI chips
52
are cascaded.
In the liquid crystal panel
54
, the number of pixels is 800 pixels×3(RGB)[source]×600 pixels[gate].
The first through eighth source drivers provide a 64-gray scale display and respectively drive 100 pixels×3(RGB).
As shown in
FIG. 11
, each of the source driver LSI chips
51
of the source drivers is constituted by a shift resister circuit
61
, a data latch circuit
62
, a sampling memory circuit
63
, a hold memory circuit
64
, a reference source generating circuit
65
, a DA converter circuit
66
, and an output circuit
67
.
In the shift resister circuit
61
, as a start pulse, a start-pulse input signal SPI (signal) is outputted from a terminal SSPI of the controller circuit
56
and inputted to a terminal SPin of the source driver LSI chip
51
in synchronization with a horizontal synchronizing signal of the image data signals R·G·B (signal). Further, afterwards, the shift resister circuit
61
shifts the start-pulse input signal SPI in response to a clock signal CK (reference signal) which is outputted from an SCK terminal of the controller circuit
56
.
The start-pulse input signal SPI, which has been shifted in the shift resister circuit
61
, is outputted from a terminal SPout of the source driver LSI chip
51
as an output of the final step and inputted to a terminal SPin of the next source driver LSI chip
51
. Moreover, the clock signal CK is inputted to an input terminal CKin, outputted from an output terminal CKout, and inputted to a terminal CKin of the next source driver LSI chip
51
.
In the same manner, the start pulse input signal SPI is shifted to the final step of the shift resister circuit
61
of the source driver LSI chip
51
in the eighth source driver shown in FIG.
10
.
Meanwhile, the image data signals R·G·B, which are respectively outputted from R·G·B terminals of the controller circuit
56
, are constituted by 6-bit R·G·B signals. As shown in
FIG. 11
, the image data signals R·G·B are respectively inputted in parallel from a terminal R
1
-
6
in, a terminal G
1
-
6
in, and a terminal B
1
-
6
in of the source driver LSI chip
51
. And then, the image data signals R·G·B are temporarily latched in the data latch circuit
62
and are transmitted to the sampling memory circuit
63
.
The sampling memory circuit
63
performs a sampling on image signal data containing 6-bit R·G·B, 18 bits in total, that are transmitted in a time division, in accordance with an output signal from each step of the shift resister circuit
61
. The sampling memory circuit
63
stores the sampled image signal data until a latch signal LS (described later), which is outputted from an LS terminal (see
FIG. 3
, an explanatory drawing of the present invention) of the controller circuit
56
, is inputted.
Next, the image signal data is inputted to the hold memory circuit
64
, and the latch signal LS latches the image signal data when the image data signals R·G·B of one horizontal period are inputted to the hold memory circuit
64
. And then, the hold memory circuit
64
holds the data until data of the next horizontal period is inputted from the sampling memory circuit
63
to the hold memory circuit
64
; meanwhile, the image signal data is outputted.
The reference source generating circuit
65
generates, for example, 64-level voltage for a gray-scale display by using a resistance division, in accordance with a reference voltage which is outputted from a terminal Vref
1
-
9
(see
FIG. 3
, an explanatory drawing of the present invention) of the controller circuit
56
and is inputted to a terminal Vref
1
-
9
of the source driver LSI chip
51
.
The DA converter circuit
66
converts digital 6-bit image signals R·G·B to analog signals. And then, the output circuit
67
amplifies the 64-level analog signals in accordance with a voltage, which is outputted from the controller circuit
56
and is inputted to a terminal VLS of the source driver LSI chip
51
, and the analog signals are outputted from output terminals XO
1
~XO
100
, YO
1
~YO
100
, and ZO
1
~ZO
100
to terminals (not shown) of the liquid crystal panel
54
.
The output terminals XO, YO, and ZO respectively correspond to the image data signals R·G·B, and each of XO, YO, and ZO has 100 terminals. Additionally, a terminal Vcc and a terminal GND of the source driver LSI chip
51
are terminals for power supplied to the source driver LSI chip
51
. Here, in
FIG. 11
, a buffer circuit is omitted.
The above description discussed the construction and operation of the source driver having a 64-step gradation.
Here, since the gate driver LSI chip
52
basically has the same construction as the source driver LSI chip
51
, the description thereof is omitted.
Regarding such a system construction of the semiconductor devices in the liquid crystal display device module, the number of pixels is increasing and resolution is becoming higher. Due to an increase in the number of pixels, the source driver LSI chips
51
and the gate driver LSI chips
52
need to realize a high-speed transmission of the image data signals R·G·B, namely, a high-frequency clock operation. This tendency is more outstanding in the source driver LSI chips
51
than in the gate driver LSI chips
52
.
For instance, when the source has 800 pixels and the gate has 600 pixels, the clock signal CK is set at nearly 65 MHz.
When the high-frequency clock signal CK is supplied to the each of the source driver LSI chips
51
via the flexible substrate
55
, stray capacitance grows so as to deform a clock waveform, resulting in a malfunction. Therefore, in the system construction of the semiconductor devices, as shown in
FIG. 10
, the adjacent TCPs
53
overlap each other so as to electrically connect wires, and the clock signal CK is outputted via the buffer circuit (not shown) in the source driver LSI chip
51
and is inputted to the next source driver LSI chip
51
. This arrangement makes it possible to successively pass the clock signal CK through all the cascaded source driver LSI chips
51
of the first through eighth source drivers.
Japanese Unexamined Patent Publication No. 3684/1994(Tokukaihei 6-3684, published on Jan. 14, 1994) discloses a method in which the adjacent TCPs
53
overlap each other so as to connect wires. In this method, a stray capacitance is small between the source driver LSI chips
51
so as to reduce
Sakaguchi Nobuhisa
Tamai Shigeki
Hjerpe Richard
Nguyen Kimnhung
Sharp Kabushiki Kaisha
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