System clock generating circuit having a power saving mode capab

Details System clock generating circuit having a power saving mode capab System clock generating circuit having a power saving mode capab

1994-05-09

1997-04-29

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327 99, 327295, 326 93, 395551, G06F 104

Patent

active

056253117

ABSTRACT:
A system clock generating circuit for supplying a system clock to a microproeessor, includes a first oscillator for generating a main clock, and a second oscillator for generating a sub clock which is lower in frequency than the main clock. A twin-clock control circuit receives the main clock and the sub clock and is controlled by the microprocessor. When the microprocessor is in an ordinary operating condition, the twin-clock control circuit generates a (n)-phase system clock which is composed of (n) clocks for each one instruction cycle, where "n" is a positive even number. When the microprocessor is in an electric power saving mode, the twin-clock control circuit also generates a (n/m)-phase system clock which is composed of (n/m) clocks for each one instruction cycle, where "m" is a positive even number but is smaller than "n".

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patent: 5483659 (1996-01-01), Yamamura

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