System clock generating circuit for a semiconductor device

Details System clock generating circuit for a semiconductor device System clock generating circuit for a semiconductor device

1996-08-05

1998-09-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

327244, 327245, 327251, H03L 706, H03L 708, H03K 506

Patent

active

058015663

ABSTRACT:
According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a phase lock loop, and receives a control voltage from the phase lock loop so as to generate a clock signal with a frequency according to the control voltage and to delay and output the clock signal. A second pulse generator generates two-phase clocks by using delayed signals generated by the second delay circuit. Switches are used for switching between a system clock output terminal during an actually active time and a system clock output terminal during testing.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 5039893 (1991-08-01), Tomisawa
patent: 5081428 (1992-01-01), Atriss et al.
patent: 5146121 (1992-09-01), Searles et al.
patent: 5428309 (1995-06-01), Yamauchi et al.
patent: 5475344 (1995-12-01), Manealtis et al.
patent: 5638019 (1997-06-01), Frankeny

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