System, circuit, and method for testing an interconnect in a mul

Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Distributive type parameters

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324652, G01B 714

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active

061114146

ABSTRACT:
A system for testing interconnects in multi-chip modules including a radio frequency resonator having a resonant circuit with a relatively high quality factor, the output of the resonant circuit being attached to a probe. Electrically coupled to the resonant circuit output is an apparatus to analyze the voltage signal output. The probe is applied to one end of an interconnect. When the probe is applied, the resonant frequency of the resonant circuit and the magnitude of the frequency response are altered due to the additional loading created by the interconnect. Due to the relatively high quality factor of the resonant circuit, the magnitude of the frequency response of the altered resonant circuit is measurably distinct from a predetermined reference magnitude at a predetermined reference frequency, thus indicating the existence of a defect. Additionally, the type of defect that exists is ascertainable by determining whether the resonant frequency of the altered resonant circuit is greater or less than the reference frequency by examining, for example, the phase response.

REFERENCES:
patent: 2320175 (1943-05-01), Dennis et al.
patent: 2424249 (1947-07-01), Miller
patent: 2431339 (1947-11-01), McCool
patent: 2482173 (1949-09-01), Hagstrum
patent: 2784375 (1957-03-01), Mehlman
patent: 3631336 (1971-12-01), Marvin
patent: 3763399 (1973-10-01), Jenkins
patent: 3840805 (1974-10-01), Martyashin et al.
patent: 5736862 (1998-04-01), Hamblin
Microelectronic (Sedra/Smith Fourth Editions) pp. 909-910 1993 (No Month Available).
Hopper, et al., "A Feasability Study for the Fabrication of Planar Silicon Multichip Modules Using Electron Beam Lithography for Precise Location and Interconnection of Chips," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 15, No. 1, Feb. 1992, pp. 97-102.
Roszel, "MCM Test Methodologies and Project Experiences," ICEMCM 95, pp. 424-427.
Berke, et al., "Test Strategy for a Microprocessor Based Multi-Chip Module," ICEMCM 95, pp. 419-423 No Month Available.
Keezer, "Electronic Test Methods for Multichip Modules," Proceedings of the 8.sup.th Electronic Materials and Processing Congress, San Jose, California, Aug. 30-Sep. 2, 1993, pp. 131-137.
Keezer, "Fault Isolation Methods for Multichip Modules," ISTFA '93: The 19.sup.th International Symposium for Testing & Failure Analysis, Los Angeles, California, Nov. 15-19, 1993, pp. 135-141.
Brunner, et al., "Contactless Testing of Multi-Chip Modules," Microelectronic Engineering 24 (1994) 61-70 No Month Available.
Brunner, et al., "Electron-Beam MCM Testing and Probing," IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B: Advanced Packaging, vol. 17, No. 1, Feb. 1994, pp. 62-68.
Zorian, "A Structured Testability Approach for Multi-Chip Modules Based on BIST and Boundary Scan," IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, vol. 17, No. 3, Aug. 1994.
Abadir, et al., "Analyzing Multichip Module Testing Strategies," IEEE Design and Test of Computers, Spring 1994, pp. 40-52 No Month Available.
Karpenske, et al., "Testing and Diagnosis of Multichip Modules," Solid State Technology, Jun. 1991, pp. 24-26.
Blood, et al., "Electrical Analysis of a Thin Film Multichip Module Substrate," IEEE 1992, pp. 138-141.
Shrivastava, "Design, Simulation Model and Measurements for High Density Interconnection," International Conference on Advances in Interconnection and Packaging (1990), vol. 1389, pp. 122-137 No Month Available.
Woodard, Sr., "High Density Interconnect Verification of Unpopulated Multichip Modules," 1991 Proceedings, Eleventh IEEE/CHMT International Electronics Manufacturing Technology (IEMT) Symposium, pp. 434-439 No Month Available.
Deutsch, et al., "Characterization of Resistive Transmission Lines by Short-Pulse Propagation," IEEE Microwave and Guided Wave Letters, vol. 2, No. 1, Jan. 1992, pp. 25-27.
Lipa, et al., "Experimental Characterization of Transmission Lines in Thin-Film Multichip Modules," IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part A, vol. 19, No. 1, Mar. 1996.
Hayden, et al., "Characterization of Multiple Line Interconnection Structures from Time Domain Measurements," ISHM '93 Proceedings, pp. 622-625 No Month Available.
Wedwick, "Testing MLBs Continuity Testing by Capacitance," Circuits Manufacturing, Nov. 1974, pp. 58, 61.
Golladay, et al., "Electron-Beam Technology for Open/Short Testing of Multi-Chip Substrates," IBM J. Res. Develop., vol. 34, No. 2/3 Mar./May 1990, pp. 250-259.
Marshall, et al., "CAD-Based Net Capacitance Testing of Unpopulated MCM Substrates," IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B: Advanced Packaging, vol. 17, No. 1, Feb. 1994.
Crnic, et al., "Electrical Test of Multi-Chip Substrates," ICEMM Proceedings '93, pp. 422-428 No Month Available.
Economikos, et al., Electrical Test of Multichip Substrates, IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B: Advanced Packaging, vol. 17, No. 1, Feb. 1994, pp. 56-61.
Ross, et al., "High Density Interconnect Verification Using Voltage Contract Electron Beam," IEEE/CHMT '91 IEMT Symposium, pp. 270-274 No Month Available.
Hamel, et al., "Capacitance Test Technique for the MCM of the 90s," Proceedings of the Technical Conference 1993 International Electronics Packaging Conference, Sep. 12-15, 1993, vol. 2, pp. 855-871.

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