System bus with separate address and data bus protocols

Details System bus with separate address and data bus protocols System bus with separate address and data bus protocols

1996-12-31

1998-04-07

Harvey, Jack B.

39520005, 39520013, G06F 1300, G06F 13368

Patent

active

057375461

ABSTRACT:
Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.

REFERENCES:
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5235685 (1993-08-01), Caldara et al.
patent: 5237567 (1993-08-01), Nay et al.
patent: 5561806 (1996-10-01), Fitchett et al.

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