System architecture for and method of dual path data processing

Details System architecture for and method of dual path data processing System architecture for and method of dual path data processing

1997-07-25

1999-06-29

Shin, Christopher B.

Multiplex communications

Wide area network

Packet switching

395822, 39520043, 395840, 395849, 370389, 370395, G06F 1300

Patent

active

059180749

ABSTRACT:
A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.

REFERENCES:
patent: 5313582 (1994-05-01), Hendel et al.
patent: 5610914 (1997-03-01), Yamada
patent: 5715407 (1998-02-01), Barth et al.
patent: 5752078 (1998-05-01), Delp et al.
patent: 5799209 (1998-08-01), Chatter

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