Patent
1995-12-29
1997-11-25
Harvey, Jack B.
395838, G06F 132
Patent
active
056922027
ABSTRACT:
A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.
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Chung Chih-Hung
Kardach James P.
Ziller Jason
Etienne Ario
Harvey Jack B.
Intel Corporation
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