System and technique for synchronizing data to instructions in a

Details System and technique for synchronizing data to instructions in a System and technique for synchronizing data to instructions in a

1996-03-22

1998-08-11

Coleman, Eric

395551, G06F 300

Patent

active

057940029

ABSTRACT:
A system and technique for synchronizing data to instructions. The inventive system (10) includes a processor (12), a first memory (14) for providing instructions to the processor (12), a second memory (16) for providing data to the processor (12); and a logic circuit (18, 20), responsive to the second memory (16), for synchronizing the input of instructions from the first memory (14) to the processor (12) based on the rate of flow of data into the second memory (16). In a particular implementation, the second memory (16) is a first-in, first-out (FIFO) memory which provides output data at a first output terminal and an `almost empty` output signal at a second output terminal thereof. The logic circuit includes an OR gate (18) having a first input terminal connected to the second terminal of the FIFO memory, a second input terminal connected to a source (22) of a clock signal and an output terminal. The logic circuit further includes a register (20) having a first input terminal connected to the first memory (14), an output terminal connected to the processor (12) and a clock input terminal connected to the output terminal of the OR gate (18). The `almost empty` signal is used to freeze the instruction stream into the processor (12) based on the state of the FIFO (16). The system is flexible and programmable yet synchronization is effected quickly and automatically with simple hardware, minimal memory and no software overhead.

REFERENCES:
patent: 4172281 (1979-10-01), Gordon
patent: 5042000 (1991-08-01), Baldwin
patent: 5179530 (1993-01-01), Genusov
patent: 5185871 (1993-02-01), Frey

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