System and methods of recovering a clock from NRZ data

Pulse or digital communications – Synchronizers – Self-synchronizing signal

Reexamination Certificate

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Reexamination Certificate

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10411996

ABSTRACT:
A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an inverted NRZ signal are received). The inverted NRZ data may be delayed by one-half of a unit interval with respect to the NRZ data by a delay element. The NRZ data and the delayed NRZ data may be combined by a broadband combiner (e.g., a resistive adder). The combined signal may be split into two signals. The two split signals may be rectified by suitable components. One of the limited split signals may be subtracted from the other limited split signal to generate an output signal. The generated output signal then possesses a spectral component at a clock frequency of the NRZ data.

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Yoo et al. , A Novel Clock Extraction Circuit Using A New NRZ-to-PRZ Converter And A Dielectric Resonator Filter For 10 Gbits/s Optical Receiver, May 16-20, 1995, Microwave Symposium Digest, 1995, IEEE MTT-S International, vol. 3, pp. 1395-1398.□□.
U.S. Appl. No. 10/412,374, filed Apr. 11, 2003, Richard K. Karlquist.

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