Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-03-16
2002-12-03
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06489834
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to management of power consumption by an integrated circuit, and in specific to a system and method that utilize on-chip voltage comparators to monitor the long-term (sustained) and short-term (instantaneous) power consumption of the chip to generate signals utilized for dynamically controlling operation of the chip in order to effectively manage its long-term and short-term power consumption.
BACKGROUND
Integrated circuits (commonly referred to as “chips”), such as microprocessors, are utilized in an ever-increasing number of various applications. For instance, such chips are commonly implemented not only in personal computers (PCs) and laptops, but are typically implemented in much smaller (and more portable) devices, such as personal digital assistants (PDAs), cellular telephones, pagers, and various other types of devices. Considering the number of tasks that such chips are relied upon to perform, the desire for fast processing speeds (to allow tasks to be performed quickly), and the desire for limited power consumption by such chips, chip designers are faced with the difficult task of designing chips that achieve the desired performance (e.g., fast processing speed), while managing the power consumption of the chips. Given the ever-increasing advances being made in performance of chips, such as microprocessors, power consumption is becoming a serious concern. For example, power consumption is becoming a serious performance limiter for high speed microprocessors. For instance, it seems that with each succeeding generation of microprocessors, on-chip voltage-supply budgets dwindle while ac current consumption increases. Thus, a key design objective for microprocessor systems is providing the highest possible peak performance for compute-intensive code, while reducing power consumption of the microprocessor system. Particularly when such microprocessor systems are to be implemented within portable electronic devices, reduction in power consumption (at least during low performance periods) is desirable to maximize the battery life of the device.
As is well known, power consumption of a chip may be generally computed utilizing the following equation: P=C*V
2
*F, wherein P represents power consumption, C represents switching capacitance, V represents operating voltage, and F represents the clock frequency of the chip. In view of such equation, it should be understood that switching capacitance (C), voltage (V), and frequency (F) are all factors in determining the power consumption (P) of a chip. In many cases, it is necessary to limit processor frequency (F) and/or voltage (V) in order to hold the power consumption (P) of a chip below a certain level that is acceptable for use in a given system (e.g., within a desktop or portable devices).
Generally, two related power consumption concerns are present in chip designs. A first concern is the long-term (or sustainable) power consumption of the chip. In this regard, “long-term” (or sustainable) power consumption encompasses micro to millisecond time frame, which may be relatively long-term in operation of some chip designs. It is generally desirable to provide a chip design that provides a relatively low sustained power consumption. As described further below, prior art chip designers typically determine the maximum power that the chip may consume during worst case operation (e.g., during very compute-intensive operation), and may establish such determined maximum power as the sustained power to be supplied to the chip in order to allow for proper operation during worst case operations.
A second concern that arises with chip design is short-term (or instantaneous) power consumption. In this regard, “short-term” (or instantaneous) power consumption encompasses nanosecond time frame. For example, a chip may, on average, require 20 watts of power, but may suddenly pull 100 watts of power. As those of ordinary skill in the art will appreciate, such a sudden step in power (e.g., a sudden step in the current load) will generally result in a droop in voltage. For instance, suppose that for all circuits on a chip to operate at a desired frequency (e.g., 1 gigahertz) the chip must receive a supply voltage above a particular minimum value, say 1 volt. Thus, in this example, if the voltage droops to 0.9 volt, then the circuits fail to operate at 1 gigahertz and the part will fail. Thus, it is necessary to ensure that the voltage does not droop below 1 volt in this example. If big step loads are encountered on the chip, then a guard band of additional voltage (above the required 1 volt) may need to be supplied to the chip. For instance, if step loads are encountered by the chip that result in a voltage droop up to 100 millivolts (i.e., 0.1 volt) at any instant, then 1.1 volts actually needs to be fed to the chip so that when a voltage droop of 0.1 volt is encountered the chip will still be supplied the necessary 1 volt to maintain proper operation at the 1 gigahertz frequency. That is, when a step load event is encountered, the voltage may droop briefly to 1 volt, and will then return to 1.1 volts. Thus, the additional 0.1 volt is required solely to guard band against step load events.
It is generally desirable to reduce the amount of sustained power required by a chip. Furthermore, it is generally desirable to reduce the amount of voltage droop that a chip encounters during operation (e.g., upon incurring step load conditions). Typically, such desires in designing chips are somewhat in conflict. For example, as a chip designer lowers the sustained power consumption of a chip, the chip generally encounters greater voltage droops (as a result of step loads). For instance, suppose a chip is designed having a sustainable power consumption of 60 watts, and from time to time briefly encounters step load conditions requiring 80 watts, thereby resulting in a voltage droop. Further suppose that the chip designer implements a design that reduces the chip's sustainable power consumption to only 20 watts. If the chip continues to encounter such step load conditions requiring 80 watts, much greater voltage droops will be recognized. Thus, while the designer has reduced the long-term, sustainable power consumption of the chip, the voltage droop encountered by the chip is much greater. Accordingly, it is often difficult to effectively manage both the long-term, sustained power consumption, as well as the short-term power consumption of a chip.
Various prior art solutions have been implemented for managing long-term (sustainable) power consumption on a chip. Microprocessor chips of the prior art have typically been implemented with a fixed voltage and frequency determined to prevent the chip from consuming more than a particular amount of power. Typically, in designing prior art microprocessor chips, a designer tests the chip with software code for creating a heavy computational load on the chip in order to determine the appropriate voltage and frequency that may be implemented for the chip such that its power consumption does not exceed a particular amount when heavy computational loads are encountered by the chip. However, once implemented, such heavy computational loads may be encountered relatively seldom, with low (or no) computational load being placed on the microprocessor much of the time. Accordingly, the worst case computational loads dictate the voltage and frequency of the chip, thereby hindering performance of the chip (e.g., because of the decreased frequency required for the worst case) and resulting in inefficient use of power (as much of the power is wasted during most of the chip's operation).
Prior art solutions have also been proposed for reducing the amount of voltage droops encountered on a chip (i.e., for managing a chip's short-term power consumption). One power-saving technique implemented in prior art microprocessor chips involves regulating the voltage of the on-chip power supply to reduce voltage droops, thereby allowing for higher clock frequency to be imple
Josephson Don D
Naffziger Samuel D.
Hewlett--Packard Company
Zweizig Jeffrey
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