Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-09-02
2001-03-27
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06209012
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system and method for speech and audio coding and, more particularly, to a system and method that uses mode bits to specify which coding standard is implemented so that the system will perform the correct data manipulation operations for that coding standard.
BACKGROUND OF THE INVENTION
Mobile communications devices such as cellular telephones communicate with telephones and computer systems using analog or digital signals at various stages of the signal transmission path. The conversion of the analog signals to the digital signals, and vice versa, is accomplished using analog-to-digital and digital-to-analog converters. The compression of speech signals is accomplished using one of several speech (and audio) coding standards.
Some of the more important coding standards include the North American cellular standards (e.g., IS54), the ITU-T standards G.723, G.728 and G.729, and the European cellular standards (GSM-EFR, GSM-FR and GSM-HR). The speech processing specifications of GSM are described, for example, in the
GSM
6.01-6.32
Recommendation Specification
document or in the book by Michel Mouly and Marie-Bernadette Pauter entitled
The GSM System for Mobile, Communications,
Palaiseau, France, ISBN 2-9507190-0-7.
Typically, these coding standards include various algorithm specifications that define how data must be manipulated so that the data conforms to the coding standard. For example, GSM is specified in a bit-exact standard that defines in detail all arithmetic operations and their required accuracy. Thus, each implementation that follows the standard will produce the same output for a given input sequence. By providing a collection of test vectors as part of the standard, compliance with GSM is easily verified.
As a result of strict specifications such as this, a given data operation may need to be implemented differently depending on the standard being applied. For example, a multiple-precision multiply operation that shifts the bits in a data word fifteen bits to the right is specified as a shift right fifteen bits operation in GSM-HR, but is specified as a shift right sixteen bits and a shift left one bit operation in GSM-EFR.
Conventionally, coding processing systems are implemented and configured for a single coding standard. That is, a given system cannot be dynamically switched between different coding standards. Thus, to provide the appropriate decoding for different coding standards, more than one coding system is required. This can significantly increase the cost to a user should he or she need to upgrade his or her system to support a different coding standard.
Thus, a need exists for a coding processing system that can conveniently and economically process signals defined according to a variety of coding formats.
SUMMARY OF THE INVENTION
Mode bits incorporated into a digital signal processor define the implementation of various data operations associated with coding standards. The digital signal processor can be reconfigured to accommodate a different coding standard simply by changing the setting of the mode bit.
In one embodiment, a shift fifteen mode bit defines whether the system performs a conventional shift right fifteen bits operation or whether it performs a shift right sixteen bits and a shift left one bit operation. By using the mode bit to specify the coding standard, the system can use a common shift fifteen instruction for both GSM-HR and GSM-EFR coding standards.
In another embodiment, a mode bit supports a shift-and-round operation. This mode bit defines whether to route the most significant bit shifted out of a data word to the carry bit of an adder in the next stage of the processing chain.
REFERENCES:
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5327543 (1994-07-01), Miura et al.
patent: 5513181 (1996-04-01), Bresalier et al.
patent: 5598362 (1997-01-01), Adelman et al.
patent: 5896305 (1999-04-01), Bosshart et al.
patent: 5978822 (1999-11-01), Muwafi et al.
patent: 5991786 (1999-11-01), Mahurin
patent: 6009451 (1999-12-01), Burns
patent: 0 718 757 A2 (1996-06-01), None
Nurmi, J. et al., “A DSP core for speech coding applications” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal processing (ICASSP), vol. 2, 19-22, Apr. 22, 1994, pp. 11-429 to 11-432.
Darby & Darby
Lucent Technologies - Inc.
Mai Tan V.
LandOfFree
System and method using mode bits to support multiple coding... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method using mode bits to support multiple coding..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method using mode bits to support multiple coding... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455504