Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-03-20
2007-03-20
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
10765556
ABSTRACT:
The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing. The present invention further provides an interconnection scheme so that a plurality of ACE devices operates under the control of a single k-node.
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patent: 6604189 (2003-08-01), Zemlyak et al.
patent: 6647429 (2003-11-01), Semal
patent: 6760833 (2004-07-01), Dowling
Coleman Eric
NVIDIA Corporation
Patterson & Sheridan L.L.P.
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