System and method to relieve ESD requirements of NMOS...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

07940501

ABSTRACT:
A system and method relieves ESD requirements on devices in circuits of chips that are susceptible to being damaged from ESD through an external pad. For example, one of the devices can be NMOS transistors having drains (or sources) connected to the external pad(s) and no (or significantly small) current flows from their drains (or sources) to the corresponding pad(s). In order to protect such a device, an ESD protecting system is coupled between the NMOS device and the pad. The ESD protecting system can include an n-type transistor or a p-type transistor.

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patent: 7515390 (2009-04-01), Wang

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