System and method to reduce metal series resistance of...

Details System and method to reduce metal series resistance of... System and method to reduce metal series resistance of...

2004-12-03

2008-10-07

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S778000

Reexamination Certificate

active

07432595

ABSTRACT:
Provided herein, in accordance with one aspect of the present invention, are exemplary embodiments of semiconductor chips having low metallization series resistance. In one embodiment, the semiconductor chip comprises a semiconductor substrate and a metallization structure formed on the semiconductor substrate; an under bump metallurgy (“UBM”) structure layer formed over the metallization structure; and a bump formed over said UBM layer; wherein the largest linear dimension of said UBM layer is larger than the diameter of said bump.

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International Search Report for PCT/US04/040698, dated Aug. 8, 2005 (2 pgs.).
Written Opinion of the International Searching Authority for PCT/US04/040698, dated Aug. 8, 2005 (4 pgs.).

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