Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-12-13
2003-11-18
Cangialosi, Salvatore (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S413000, C370S419000
Reexamination Certificate
active
06650651
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to packet switches, and particular to a system and method to implement a packet switch output buffer.
BACKGROUND
Packet switches are typically implemented within the various layers of a standard Open System Interconnection (OSI) Model which general networks use in order to allow data communication within a network environment. The typical packet switches contained in the standard OSI Model network are designed to provide the three lower layer services to the respective subscribers (i.e., physical layer, data link layer and network layer).
Accordingly, data packets or data cells are routed through the various layers of the OSI Model network by the respective packet switches of the standard network system. As data packet traffic within a network system increases, the need for a high data packet transfer rate becomes increasingly important to the proper overall operations of the network. It is therefore desirable to provide a packet switch that can provide a high data packet transfer rate.
SUMMARY OF THE INVENTION
The present invention provides a system and method to implement a packet switch output buffer. Incoming data packets are temporarily stored in an input buffer memory. Data packets in the input buffer memory are then examined to determine locations in an output buffer memory where the data packets should be transferred. Data packets in the input buffer memory are then transferred to the output buffer memory, such that data packets destined for a line card are written in an output memory block corresponding to the line card. Afterward, data packets in the output buffer memory are extracted and forwarded.
In accordance with one embodiment of the present invention, an output buffer in a packet switch includes an output buffer memory that is configured to store data packets. The output buffer memory includes number of output memory blocks. Each of the output memory blocks configured to store data packets destined for a corresponding line card. The output buffer further includes a scheduler coupled to the output memory to extract data packets stored in the output buffer memory.
REFERENCES:
patent: 4500987 (1985-02-01), Hasegawa
patent: 5402416 (1995-03-01), Cieslak et al.
patent: 5406556 (1995-04-01), Widjaja et al.
patent: 5440553 (1995-08-01), Widjaja et al.
patent: 5612952 (1997-03-01), Motoyama
patent: 5872787 (1999-02-01), Cooperman et al.
patent: 6032205 (2000-02-01), Ogimoto et al.
patent: 6192422 (2001-02-01), Daines et al.
Achilles Heather
Fortuna Mike
Gallo Paul
Meredith Jim
Yin Nanying
Blakely , Sokoloff, Taylor & Zafman LLP
Cangialosi Salvatore
Nortel Networks Limited
LandOfFree
System and method to implement a packet switch output buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method to implement a packet switch output buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method to implement a packet switch output buffer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3145622