Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-12-13
2004-01-13
Cangialosi, Salvatore (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S419000
Reexamination Certificate
active
06678279
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to packet switches, and particular to a system and method to implement a packet switch buffer for unicast and multicast data.
BACKGROUND
Packet switches are typically implemented within the various layers of a standard Open System Interconnection (OSI) Model which general networks use in order to allow data communication within a network environment. The typical packet switches contained in the standard OSI Model network are designed to provide the three lower-layer services to the respective subscribers (namely a physical layer, a data link layer, and a network layer).
Accordingly, data packets or data cells are routed through the various layers of the
0
SI Model network by the respective packet switches of the standard network system. As data packet traffic within a network system increases, the need for a high data packet transfer rate becomes increasingly important to the proper overall operations of the network. It is therefore desirable to provide a packet switch that can provide a high data packet transfer rate.
SUMMARY OF THE INVENTION
The present invention provides a system and method to implement a packet switch buffer for unicast and multicast data. Incoming data packets are first stored in an input buffer memory. These data packets are examined to determine where in a primary output memory to place the data packets. The data packets are then transferred from the input buffer memory to the primary output memory. Afterward, the data packets are transferred from the primary output memory to a secondary output memory, and then from the secondary output memory to line card interface units (LCIUs).
In accordance with one embodiment of the present invention, an output buffer system includes a primary output memory to store data packets. The output buffer system also includes a secondary output memory, which is configured to store data packets transferred from the first output memory. In addition, the output buffer system includes a scheduler, which is coupled between the primary output memory and the secondary output memory. The scheduler facilitates the transfer of data packets from the primary output memory to the secondary output memory.
The above described and many other features of the present invention will become apparent as the invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings.
REFERENCES:
patent: 4500987 (1985-02-01), Hasegawa
patent: 5235595 (1993-08-01), O'Dowd
patent: 5361256 (1994-11-01), Doeringer et al.
patent: 5406556 (1995-04-01), Widjaja et al.
patent: 5440553 (1995-08-01), Widjaja et al.
patent: 5517494 (1996-05-01), Green
patent: 5535197 (1996-07-01), Cotton
patent: 5805589 (1998-09-01), Hochschild et al.
patent: 6032205 (2000-02-01), Ogimoto et al.
patent: 6192422 (2001-02-01), Daines et al.
patent: 6275491 (2001-08-01), Prasad et al.
patent: 6337860 (2002-01-01), Wicklund
Achilles Heather
Fortuna Mike
Gallo Paul
Meredith Jim
Yin Nanying
Blakely , Sokoloff, Taylor & Zafman LLP
Cangialosi Salvatore
Nortel Networks Limited
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