Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-04-10
2007-04-10
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S002000, C703S003000, C703S017000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10334113
ABSTRACT:
Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, e.g., VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.
REFERENCES:
patent: 6185516 (2001-02-01), Hardin et al.
patent: 6247163 (2001-06-01), Burch et al.
patent: 6618841 (2003-09-01), Huang
patent: 6691078 (2004-02-01), Beer et al.
patent: 6751582 (2004-06-01), Andersen et al.
patent: 6848088 (2005-01-01), Levitt et al.
patent: 6975976 (2005-12-01), Casavant et al.
patent: 2002/0055829 (2002-05-01), Rajan
patent: 2002/0095645 (2002-07-01), Rodeh
patent: 2002/0138812 (2002-09-01), Johannsen
patent: 2002/0144236 (2002-10-01), Beer et al.
patent: 2003/0182638 (2003-09-01), Gupta et al.
patent: 2005/0043935 (2005-02-01), Dreschsler et al.
E.M. Clarke et al., “Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking”, 32nd ACM/IEEE Design Automation Conference, 1996, pp. 1-6.
Scott Hazelhurst and Carl-Johan H. Seger, “Symbolic Trajectory Evaluation”, T. Kropf (E), Formal Hardware Varification; Methods and Systems in Comparison, LNCS 1287, Springer-Verlag, Berlin, Aug. 1997, pp. 1-69.
Dong Wang et al., “Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines”, Proceedings of DAC, 2001, pp. 1-6.
Edmund Clarke et al., “Counterexample-Guided Abstraction Refinement”, Proceedings of CAV, 2000, pp. 1-16.
Ranan Fraer et al., “Evaluating Semi-Exhaustive erification Techniques for Bug Hunting”, Proceedings of SMC, 1999, pp. 1-11.
Fraer Ranan
Glusman Marcelo
Irron Amitai
Kamhi Gila
Mador-Haim Sela
Pearl Cohen Zedek Latzer, LLP.
Rodriguez Paul
Thangavelu K
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