System and method testing computer memories

Details System and method testing computer memories System and method testing computer memories

1995-06-07

1998-04-21

Nguyen, Hoa T.

Excavating

371 225, 371 226, 371 211, 39518306, 39518318, G01R 3128

Patent

active

057426163

ABSTRACT:
A self test circuit provides a general statement about the condition of a coupled memory which indicates whether a wanted or unwanted manipulation or alteration of the memory has occurred. The contents of the memory are not derivable from the general statement. The general statement is preferably a "fail" or "pass" statement stating whether a deviation in the contents of the memory with respect to a last executed test has been detected or not. The testing of a non-volatile memory is executed by generating a signature from the contents of the non-volatile memory and comparing the generated signature with a reference value of the signature. When the comparison of the generated signature with the reference value indicates a different, a signal is issued and access to the non-volatile memory is restricted and/or a failure procedure is started. Access to the non-volatile memory is allowed when the comparison signature with the reference value indicates no difference. In order to allow a test of whether an alteration of the contents of the non-volatile memory has happened between successive authorized applications, a new signature from the contents of the non-volatile memory is generated after each application and stored as a new reference value.

REFERENCES:
patent: 4727544 (1988-02-01), Brunner et al.
patent: 4816656 (1989-03-01), Nakano et al.
patent: 4930129 (1990-05-01), Takahira
patent: 5436971 (1995-07-01), Armbrust et al.

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