Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-10-09
2004-01-27
Assouad, Patrick (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S058000, C702S081000, C702S189000, C365S189011, C365S189070, C365S189090, C365S189110, C714S774000, C714S799000, C711S102000, C711S103000, C324S076610, C324S211000
Reexamination Certificate
active
06684173
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to floating gate memory cells.
BACKGROUND OF THE INVENTION
One class of integrated circuits contains floating-gate memory devices that utilize electron tunneling to either add electrons to, or remove electrons from, the floating gates. In other words, electron tunneling is employed to either program and/or erase those cells. Such ICs are often called EEPROMs, flash EPROMs, or non-volatile RAMS. Floating gate cells which rely on tunneling may also be used in other types of integrated circuits as well.
One predominant reliability failure mechanism has plagued floating gate devices in the past. This is the inability of the memory cell to continue to program and erase (typically referred to on an EPROM type device as “cycling” or “endurance”). An IC failing after a given cycling operation is frequently referred to as suffering an “endurance failure”. Note that the term “reliability” as used in this context, refers to the probability that an IC will perform a required function for a stated period of time. Common causes of cycling failure include rupture of the tunneling oxide, excessive electron/hole trapping in the tunneling oxide, ion contamination or failure of the conductive circuit elements (made of metal, semiconductor or contact between the two) to the sensing circuitry located outside the memory array.
In the past, once a floating-gate circuit has been completely fabricated, there has no been a way of predicting how many cycles that part may endure before failing to erase or program. Consequently, manufacturers have had to implement elaborate screening procedures to eliminate those devices that are destined to fail within a relatively short period of time. The traditional method of screening dielectric breakdown endurance failures involves extensive program/erase cycling of the ICs. The devices in question, or a statistical sample of them, are cycled many times and then tested for proper functionality. This type of screening generally involves discarding the failed ICs. Alternatively, the IC may be repaired using redundant circuitry that can be switched in to replace defective circuit elements. Lot/acceptance criteria may also be used so that an entire lot of wafers may be rejected based upon the percent fail in the cycling screen or some other measure of endurance of the lot or the samples taken from it.
See “Method of screening EPROM-related devices for endurance failure”, U.S. Pat. No. 4,963,825 issued Oct. 16, 1990 for a method for screening EPROM-related integrated circuits for endurance failures. The screening method is based on a measurement of the number and distribution of cells within the EPROM-related device which program and/or erase significantly further and faster than “normal” cells.
Standard abnormal memory cell screens involve either limiting the number or program or erase pulses allowed for the cells to achieve a programmed or erased state or fully or partially programming/erasing the cells and then screening for cells outside an acceptable Vt distribution, as described above. In both cases, all cells are biased during program/erase verification with nominal drain voltage and compared for cell current (Ids) against a reference cell that is slightly above (programmed Vt) or below (erased Vt) the nominal read reference cell Vt by a few &mgr;A.
Endurance cycling of memory cells has shown that cells, which pass traditional screening tests, can intermittently fail to erase. Additionally, test data has shown that cells that pass this test may intermittently fail repeated or long reads.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved testing procedures to identify problem memory cells.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of testing a non-volatile floating gate memory cell comprises placing the memory cell in a low threshold voltage, Vt, state, applying a normal read level drain voltage to a drain of the memory cell, applying an elevated gate voltage to a control gate of the memory cell, and comparing a drain current of the memory cell to a reference drain current. The memory cell is determined to be defective if the drain current is below the reference current.
In another embodiment, a method of testing a non-volatile floating gate memory cell comprises placing the memory cell in a low threshold voltage, Vt, state, applying a reduced drain voltage to a drain of the memory cell, and applying a nominal or elevated gate voltage to a control gate of the memory cell. A drain current of the memory cell is compared to a reference drain current, wherein the memory cell is determined to be defective if the drain current is below the reference current.
A method of testing a non-volatile floating gate memory cell comprises placing the memory cell in a low threshold voltage, Vt, state, applying a drain voltage in the range of 0.5 to 2.5 volts to a drain of the memory cell, and applying a gate voltage in the range of 2.0 to 12 volts to a control gate of the memory cell. A drain current of the memory cell is compared to a reference drain current in the range of 10 &mgr;A to 200 &mgr;A, wherein the memory cell is determined to be defective if the drain current is below the reference current.
A method of testing a non-volatile floating gate memory cell comprises placing the memory cell in a low threshold voltage, Vt, state, applying a drain voltage in the range of 0.1 to 1.0 volts to a drain of the memory cell, and applying a gate voltage in the range of 0.0 to 12 volts to a control gate of the memory cell. A drain current of the memory cell is compared to a reference drain current in the range of 1 &mgr;A to 100 &mgr;A, wherein the memory cell is determined to be defective if the drain current is below the reference current.
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Sweetman, Reliability of Reprogrammable Nonvolatile Memories Jan. 1998, Vol: 4518, pp. 101-108.
Batutis Devin
Kessenich Jeffrey Alan
Mihnea Andrei
Assouad Patrick
Desta Elias
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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