Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2005-06-21
2005-06-21
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
Reexamination Certificate
active
06910121
ABSTRACT:
A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. The method entails determining whether to copy the register value generated by executing an instruction from the alias register to the real register at the time the reorder buffer entry associated with the alias register is needed for a new instruction. If before the reorder buffer is needed for a new instruction, an interim instruction resulted in a new register value for the real register, then the original register value would be invalid at the time the reorder buffer entry is needed for the new instruction. Thus, there would not be a need to copy the original register value to the real register. The reduction in copying can make the processor system consume less power.
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C. Molina, et al., “Reducing Memory Traffic Via Redundant Store Instructions”, In Proceedings of the international Conference on High Performance Computing and Networking, Apr. 1999.
Kevin M. Lepak, et al. “On the Value Locality of Store Instructions”, In Proceedings of the 27th Annual International Symposium on Computer Architecture, Jun. 2000.
Ronen Ronny
Savransky Guillermo
Blakely , Sokoloff, Taylor & Zafman LLP
Coleman Eric
Intel Corporation
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