System and method of measuring low impedances

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C702S064000, C702S077000

Reexamination Certificate

active

06768952

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits, and in particular to a method of measuring low impedances.
BACKGROUND OF THE INVENTION
Several factors in the development of computer systems and electronic circuits such as microprocessor chips, printed circuit boards, and electronic packaging contribute to the need for lower impedances over a wide bandwidth in the power distribution networks of these systems. Decreasing power supply levels, signal transition times and die sizes, and the steady increase of power supply currents and clock speeds all require the power distribution network to have very low impedance levels. The typical target impedance for computer systems have decreased by a factor of five every two years. Low impedance in the milliohm and sub-milliohm range is desirable to minimize noise generation, electromagnetic radiation and interference.
While techniques to verify signal integrity of high-speed signals have been widely available, the need to accurately measure very low impedances in the milliohm and sub-milliohm ranges at high frequencies remains unsatisfied. Time-domain reflectometry instruments have been used to measure power distribution network impedances. However, time-domain reflectometry measurements are not suitable for measuring milliohm range impedances due to the noise and nonlinearity of the oscilloscope used in this method. RLC (resistance, inductance and capacitance) meters cannot measure sub-ohm impedances at hundreds of megahertz frequencies. Vector network analyzers have also been used to measure circuit parameters, however they can only access exterior points of a semiconductor chip and cannot measure interior impedances. Furthermore, vector network analyzers measure impedance by supplying and forcing a current into the system, but the current cannot be pushed through the circuit uniformly and achieve satisfactory measurements. A common disadvantage of these conventional methodologies also includes the inability to obtain on-die impedance measurement during system operations.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a method of measuring impedance in a system having a microprocessor comprises holding the microprocessor in reset mode and providing a clock to the microprocessor at frequency FCLK while measuring a first current level, providing the clock at frequency FCLK/N and measuring a second current level, where N is a positive integer. While holding the microprocessor in reset and toggling the clock frequency between FCLK and FCLK/N, and generating a periodic current waveform, measuring the voltage at at least one port in the system a plurality of times to obtain a plurality of sets of voltage measurements. The plurality of sets of voltage measurements are averaged. The method further comprises varying FCLK and determining a Fourier component of the averaged voltage measurements to determine clock frequency-dependent noises, and removing the clock frequency-dependent noises to generate a filtered average voltage, and determining an impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.
In accordance with a further embodiment of the present invention, a method of determining impedance in a system having a microprocessor comprises generating a step waveform in the microprocessor by holding the microprocessor in reset mode and providing a clock to the microprocessor first at frequency F
CLK
while measuring a first current level, and providing the clock at F
CLK
/N while measuring a second current level. The method further comprises holding the microprocessor in reset mode, toggling the clock frequency between F
CLK
and F
CLK
/N, while measuring the voltage at a plurality of ports in the system to obtain a plurality of sets of voltage measurements, and averaging the plurality of sets of voltage measurements. The method comprises varying F
CLK
and determining clock frequency-dependent noises, and removing the clock frequency-dependent noises to generate a filtered average voltage, and determining an impedance as a function of frequency by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.
In accordance with yet another embodiment of the present invention, a system comprises means for holding the microprocessor in reset mode and measuring a first current level while providing a clock to the microprocessor at frequency F
CLK
, and measuring a second current level while providing the clock at frequency F
CLK
/N, means for generating a periodic current waveform and measuring the voltage at at least one port in the system a plurality of times to obtain at least one set of voltage measurements while holding the microprocessor in reset mode and toggling the clock frequency between F
CLK
and F
CLK
/N, and means for averaging the plurality of sets of voltage measurements. The system further comprises means for varying F
CLK
and determining a Fourier component of the averaged voltage measurements to determine clock frequency-dependent noises, and removing the clock frequency-dependent noises to generate a filtered average voltage, and means for determining an impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.


REFERENCES:
patent: 4196475 (1980-04-01), Hall
patent: 5203000 (1993-04-01), Folkes et al.
patent: 5627476 (1997-05-01), Chambers
patent: 5828822 (1998-10-01), Ernst
patent: 5963023 (1999-10-01), Herrell et al.
patent: 6160382 (2000-12-01), Yoon et al.
patent: 0272036 (1988-06-01), None
patent: WO 00/55639 (2000-09-01), None
Taylor, Greg et al., “An Approach to Measuring Power Supply Impedance of Microprocessors,” IEEE, 2001, pp. 211-214, no month.
Isaac Kantorovich, et al., “Measurement of Milliohms of Impedance at Hundred MHz on Chip Power Supply Loop,” Electrical Performance on Electronic Packaging Conference, Presented on Oct. 23, 2002, 4 pages.
Chris Houghton, et al., “Modeling and Measurement of the Alpha 21364 Package,” Compaq Inspiration Technology, EPEP 2001, Oct. 31, 2001, 29 pages.
Sungjun Chun, et al., “Model to Hardware Correlation for Power Distribution Induced I/O Noise in a Functioning Computer System,” Electronic Components & Technology Conference, May 2002, pp. 319-324.
Istvan Novak, “Probes and Setup for Measuring Power-Plane Impedances with Vector Network Analyzer,” 1999 High-Performance Systems Design Conference, Feb. 1-4, 1999, pp. 201-215.
Istvan Novak, “Measuring MilliOhms and PicoHenrys in Power-Distribution Networks,” 2000 High-Performance System Design Conference, Feb. 1-4, 2000, 14 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method of measuring low impedances does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method of measuring low impedances, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method of measuring low impedances will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3257957

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.