System and method of forming a tungstein plug

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S753000, C257S763000, C257S767000

Reexamination Certificate

active

06215186

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to the field of electronic devices, and more particularly to a system and method of forming a tungsten plug.
BACKGROUND OF THE INVENTION
The density of microelectronic devices on a semiconductor substrate may be increased by decreasing the size or line width of the microelectronic devices. The decrease in line width allows a large number of microelectronic devices to be formed on the semiconductor substrate. As a result, the computing's power and speed of the semiconductor combined maybe greatly improved.
In order to decrease the line width of a microelectronic device, the lateral dimensions of conductor, semiconductor and insulator regions forming each a microelectronic device must be reduced. For example, the lateral width of structures such as vias and interconnects must be reduced in order to achieve microelectronic devices of reduced geometries. Conductive vias and interconnects are utilized within microelectronic devices to form contact openings that allow an overlying conductive layer to electrically contact an underlying conductive layer through an intermediate layer such as a dielectric layer. Such contact openings may be filled with plugs of conductive material designed to electrically connect the two conductive layers.
One commonly used conductive material in plug applications designed to fill contact openings is tungsten. The formation of tungsten plug structures requires first depositing a layer of barrier material such as titanium nitride (TiN) to avoid damaging a titanium adhesion layer typically present where the contact opening meets the substrate. An undamaged adhesion layer is essential to provide a low contact resistance between a plug and the underlying substrate. Traditionally, increasing the thickness of the barrier layer was seen as a viable means of insuring that the adhesion layer remained free of defects during plug formation. However, as the lateral dimensions of contact openings continue to decrease, the via resistance of such openings reaches a prohibitive level if a significant portion of their widths are taken up with the thickness of the barrier layer. A problem therefore arises as to how to maintain the protective characteristics of the barrier layer at the significantly reduced thicknesses demanded by ever shrinking device geometries.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a structure and method for forming tungsten plugs in contact openings utilized in smaller device geometries that avoids defects in the adhesion layers present within those contact openings. In accordance with the teachings of the present invention, a structure and method of forming tungsten plugs is provided that avoids damage to the adhesion layers needed to provide effective conductive interconnects.
According to one embodiment of the present invention, an electronic device is provided that compromises a dielectric layer disposed outwardly from a substrate. The dielectric layer has at least one contact opening formed through the dielectric layer. The device has an adhesion layer disposed outwardly from the exposed surfaces of the dielectric layer and the substrate. A first barrier layer is formed outwardly from the adhesion layer. A second barrier layer is formed outwardly from the first barrier layer. A conductive plug fills the contact opening and is disposed outwardly from the second barrier layer.
The disclosed invention offers many technical advantages. For example, the invention enables the use of tungsten interconnects in reduced device geometries. In addition, the disclosed invention prevents electromigration problems in devices that utilize tungsten plugs to connect conductive layers. The invention also reduces via and contact resistance in such devices. A further technical advantage of the disclosed invention is that the invention allows for a minimization of metal stack height in conductive interconnects. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.


REFERENCES:
patent: 5449954 (1995-09-01), Ito
patent: 5624870 (1997-04-01), Chien et al.
patent: 5652464 (1997-07-01), Liao et al.
patent: 5920122 (1999-07-01), Matsumoto et al.

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