System and method of enhancing alignment marks

Details System and method of enhancing alignment marks System and method of enhancing alignment marks

2005-10-11

2005-10-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S622000, C257S623000, C257S618000

Reexamination Certificate

active

06954002

ABSTRACT:
A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

REFERENCES:
patent: 5682243 (1997-10-01), Nishi
patent: 6242754 (2001-06-01), Shiraishi
Zaidi, Saleem H., et al.,Characterization of Si Nanostructured Surfaces, SPIE Conference on Engineered Nanostructural Films and Materials, Denver, Colorado, Jul. 1999, pp. 151-159.
Hadobas, K., et al.,Reflection Properties of Nanostructure-arrayed silicon surfaces, Nanotechnology 11 (2000) 161-164.

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