System and method of correcting errors in SEM-measurements

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification

Reexamination Certificate

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C716S050000, C716S053000, C716S054000

Reexamination Certificate

active

07930654

ABSTRACT:
Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by extracting feature edges of a test pattern within an image, calculating at least one scaling error of the image by comparing the extracted feature edges of assist structures with a layout pattern, modifying feature edges of test structures within the test pattern by incorporating the at least one scaling error so as to at least partially compensate the scaling errors, and verifying a model for optical proximity corrections and/or model input data by using the modified feature edges of the test structures.

REFERENCES:
patent: 6709793 (2004-03-01), Brankner et al.
patent: 6727028 (2004-04-01), Kotani et al.
patent: 7506285 (2009-03-01), Al-Imam et al.
patent: 7519943 (2009-04-01), Futatsuya

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