System and method generating a delayed clock output

Details System and method generating a delayed clock output System and method generating a delayed clock output

2006-03-14

2006-03-14

Kinkead, Arnold (Department: 2817)

Oscillators

Combined with particular output coupling network

C331S057000, C331S045000, C375S354000, C327S291000, C713S400000, C713S500000, C713S501000, C713S503000

Reexamination Certificate

active

07012474

ABSTRACT:
The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.

REFERENCES:
patent: 5268656 (1993-12-01), Muscavage

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