System and method for Y-decoding in a flash memory device

Details System and method for Y-decoding in a flash memory device System and method for Y-decoding in a flash memory device

2006-11-28

2006-11-28

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185020, C365S185030, C365S185210, C365S185260

Reexamination Certificate

active

07142454

ABSTRACT:
A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

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