System and method for writing mixed interleaved and non-interlea

Details System and method for writing mixed interleaved and non-interlea System and method for writing mixed interleaved and non-interlea

1996-05-14

2000-08-22

Pham, Chi H.

Pulse or digital communications

Transceivers

Modems

711 5, 711157, H04B 140, G06F 1200

Patent

active

061083712

ABSTRACT:
A modem having an interactive clearing circuit that provides the facility for the modem to mix interleaved and non-interleaved writes to a FIFO without timing problems or data transfer problems associated with the prior art. The circuit includes a self-clearing error bit circuit that clears the error bits of an interleaved write from the LSR after each FIFO write. In one embodiment, the clearing circuit provides dummy bits to the LSR upon each controller write to the FIFO. This prevents error bits associated with previous interleaved writes from becoming associated with subsequent non-interleaved writes.

REFERENCES:
patent: 5623449 (1997-04-01), Fischer et al.
patent: 5664116 (1997-09-01), Gaytan et al.

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