Data processing: measuring – calibrating – or testing – Measurement system – Orientation or position
Reexamination Certificate
1999-03-11
2001-07-31
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Orientation or position
C702S155000, C355S053000, C356S401000, C430S022000
Reexamination Certificate
active
06269322
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a system and method for wafer alignment which mitigates effects of reticle rotation and magnification on overlay.
BACKGROUND OF THE INVENTION
The tendency of semiconductor devices such as integrated circuits (IC) and large scale integrated circuits (LSIC) toward minuteness has rapidly progressed, and higher accuracy has been required of apparatuses for manufacturing such semiconductor devices. In particular, such requirements are demanded from exposure devices in which a circuit pattern of a mask or a reticle is superposedly transferred onto a circuit pattern formed on a semiconductor wafer. It is desired that the circuit pattern of the mask and the circuit pattern of the wafer be superposed one upon the other, for example, with accuracies of less than 0.1 &mgr;m.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coating, etching, and deposition. In many of these steps, material is overlayed or removed from the existing layer at specific locations in order to form desired elements of the integrated circuit. Proper alignment of the various process layers is important. The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy. If proper alignment tolerances are not achieved, device defects can result.
More particularly, during fabrication of an IC, a wafer lithography system projects a pattern of light onto a photoresist layer of a wafer. The projected light changes properties of exposed portions of the photoresist layer such that a subsequent development process forms a mask from the photoresist layer which exposes or protects different portions of the wafer. The masked wafer is then removed to a reaction chamber where a process such as etching changes the exposed portions of the wafer. Typically, a wafer lithography system forms several masks on a wafer during an IC fabrication process, and the masks must be aligned with each other to form a working IC.
A wafer stepper typically is used to align the wafer during the various process steps. The wafer stepper uses one of a number of commercially available techniques to generate alignment signals which indicate position relative to the wafer. The alignment signals typically are produced by optical measurement of alignment marks placed at specified locations on the wafer. A reticle is used to place the appropriate marks on a particular wafer process layer such that the marks can be readily identified by the wafer stepper in subsequent processing steps. The reticle includes a pattern which can be etched into the wafer using optical photolithography. Commonly used alignment mark techniques include Laser Step Alignment (LSA), Field Image Alignment (FIA), Laser Interferometric Alignment (LIA), Global Alignment Mark (GAM), and Global Alignment Mark Laser Step Alignment (GAMLSA). In a step-and-repeat type apparatus, the wafer is moved in steps by predetermined distances. For example, the wafer typically is placed on a two-dimensionally moveable stage and positioned relative to a projected image of a reduction projection type exposure apparatus.
For some types of alignment systems and/or methods, in order to align the wafer large global alignment marks typically are employed. For such systems and/or methods a reticle
30
(
FIG. 1
) includes a design pattern
32
and an alignment mark
34
outside of the design pattern
32
. The alignment mark
34
may be located within the design region
32
but at the expense of sacrificing design area real estate. The design pattern
32
and alignment mark
34
are printed at several predetermined areas of a wafer
40
(FIG.
2
). These printed alignment marks are found by a stepper system (not shown) and are employed in wafer alignment, for example, for subsequent processing. However, the reticle
30
may have been in the projection system with a slight rotation and/or the reticle
30
may include rotation errors due to the alignment mark
34
and the design pattern
32
being slightly rotated (for example, as a result of error in the process of manufacturing the reticle). The errors due to rotation of the mark
34
and design pattern
32
become greatly exaggerated as one moves away from the center of the reticle
30
in the case of the aforementioned reticle manufacturing error. Another type of error is lens magnification error wherein the image (alignment mark and/or design pattern) are slightly over-magnified or under-magnified with respect to an intended magnification level. The reticle rotation error and/or lens magnification error results in the alignment mark being printed at locations different from intended.
FIG. 3
illustrates alignment mark print errors (on an exaggerated scale since a shift around 20 nm typically is observed) due to reticle rotation error. The hatched marks
44
represent intended locations for printing the alignment mark
34
on the wafer. The solid marks
48
represent actual print locations of the alignment marks
34
. The deviation from intended print location to actual print location results in overlay error since alignment of the wafer
40
is typically premised on the alignment mark
34
actually having been printed at an intended location. As noted above, proper alignment tolerances are required in order to avoid device defects resulting from overlay error. Consequently, there is a need for a system and/or method for mitigating overlay error due to reticle rotation errors and/or lens magnification/demagnification errors.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for mitigating overlay error in the production of semiconductor devices. According to one aspect of the invention, a reticle is provided with a design region and at least first and second alignment marks. The first and second alignment marks are symmetric to each other such that the center of the reticle is also a mid-point of the first and second alignment marks. The first alignment mark is printed on a surface layer of a wafer, and the second alignment mark also is printed on the surface layer of the wafer at a predetermined offset from the first alignment mark. Any reticle rotation error will result in the marks being printed at locations different from the intended locations. The print error will be in proportion to the reticle rotation error. Likewise, any lens magnification/demagnification error in the print process will result in the marks being printed at locations different from intended locations, and the print error will be in proportion to the magnification/demagnification error. However, since the first and second alignment marks on the reticle are symmetric to each other with the reticle center being a midpoint of the first and. second alignment marks, the print error of each mark will be a negative of the other such that a mid-point of the marks as printed will be substantially at the same location as a midpoint of the marks if printed without reticle rotation error and/or magnification/demagnification error.
The midpoint of the marks as printed is used as a reference point for wafer alignment as opposed to the actual marks. Reticle errors and/or lens magnification errors do not manifest in the midpoint of the first and second alignment marks as printed because of the negation effect of the two marks due to their symmetry. A wafer alignment system in accordance with the present invention maps to the midpoint of the first and second marks as printed and employs this midpoint (virtual mark) as a reference point for wafer alignment. This wafer alignment methodology is performed for a plurality of layers and mitigates overlay errors for the respective layers. It is to be appreciated that alternatively the virtual mark is not employed, but the symmetry of the alignment marks alone is utilized in compensationing for reticle rotation error.
Another aspect of the present invention employs a reticle with first and second alignment marks whic
Early Kathleen R.
Manchester Terry
Rangarajan Bharath
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Shah Kamini
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