System and method for wafer acceptance test configuration

Details System and method for wafer acceptance test configuration System and method for wafer acceptance test configuration

2005-08-16

2005-08-16

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

C702S084000

Reexamination Certificate

active

06929962

ABSTRACT:
A system for WAT (Wafer Acceptance Test) configuration. The system comprises an input/output device, a storage device, and a processor. The input/output device receives a first WAT model and qualification criteria. The storage device stores a preset WAT model and qualification criteria. The processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.

REFERENCES:
patent: 6586265 (2003-07-01), Chiou et al.
patent: 6615157 (2003-09-01), Tsai

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