System and method for verifying race-driven registers

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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C716S100000, C716S101000, C716S103000, C716S104000, C716S107000, C716S110000, C716S111000, C716S112000, C716S116000, C716S117000, C716S118000, C716S136000

Reexamination Certificate

active

07966591

ABSTRACT:
Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have not used a property instance entering the expired state, and computing a new solution space based on the current solution space and target transition.

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