Patent
1994-12-29
1997-03-25
Teska, Kevin J.
G07C 508
Patent
active
056153570
ABSTRACT:
A method of adapting execution-driven simulators to accept traces is provided. First, a benchmark program is executed to provide a trace file of the executed instructions. Each output instruction of the trace file includes the program counter (PC) and the op code of the instruction executed. In addition for memory access instructions, the trace file includes effective memory addresses, and for decision control transfer instructions, the trace file includes actual branch destinations. Next, the trace file is randomly sampled to produce relatively small segments of contiguous trace instructions. These are then provided to a processor model which processes them concurrently with the benchmark program which is provided in a memory model connected to the processor model. To ensure that the processor design performance is accurately predicted, the trace file effective addresses are used during execution. After each instruction in the trace file has been processed, the processor performance statistics such as average cycles per instruction and cache hit rate are provided.
REFERENCES:
patent: 4500993 (1985-02-01), Jacobson
patent: 5088058 (1992-02-01), Salsburg
patent: 5146586 (1992-09-01), Nakano
patent: 5446876 (1995-08-01), Levine et al.
patent: 5448713 (1995-09-01), Hamamoto
Voith, Raymond, P.; "The Power PC.TM. 603 C++ Verilog.TM. Interface Model, Motorola MMTG Software Group"; pp. 337-340; IEEE; 1994.
Lauterbach, Gary, "Accelerating Architectural Simulation by Parallel Execution of Trace Samples", pp. 1-13, Sun Microsystems Laboratories, Inc., Dec. 1993.
Cmelik, Bob, Keppel, David, "Shade: A Fast Instruction-Set Simulator for Execution Profiling", pp. 128-137, Sigmetrics, Santa Clara, 1994.
Poursepanj, Ali, Ogden, Deene, Burgess, Brad, Sonya, Gary, Dietz, Carl, Lee, David, Sutya, S., Peters, Mike, "The Power PC.TM. 603 Microprocessor: Performance Analysis and Design Trade-offs", pp. 316-323, Motorola, Inc., Austin, TX, 1994.
Fiul Dan
Sun Microsystems Inc.
Teska Kevin J.
LandOfFree
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