Boots – shoes – and leggings
Patent
1995-03-21
1997-04-15
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364578, G06F 1750, G06G 748
Patent
active
056216521
ABSTRACT:
An apparatus and method for verifying a semiconductor process model. The apparatus consists of an atomic force microscope (AFM), a semiconductor process model and a model updater. The AFM measures an actual cross sectional profile of a submicron semiconductor device feature created by an IC processing step which could be photolithography. The semiconductor process model predicts the feature's cross sectional profile under a set of model conditions specified to match the actual conditions under which the IC processing step took place. The semiconductor process model is driven by a set of model parameters that relate feature profiles to processing conditions and details of the processing step being modelled. The model updater adjusts, if necessary, the model parameters of the semiconductor process model so that the predicted profile more closely approximates the actual cross sectional profile. If the parameters are adjusted, the process model generates an updated predicted profile, which the model updater again compares to the actual profile. This process iterates until the model updater determines that the predicted and actual profiles are suitably correlated, at which point the process model is verified. Once verified, the process model of the present invention can be configured to output a sequence of processing steps compatible with an IC manufacturing process. Thus, the verified process model can specify the steps by which a device characterized by a specified profile can be manufactured.
REFERENCES:
patent: 4894790 (1990-01-01), Yotsuya et al.
patent: 5307296 (1994-04-01), Uchida et al.
patent: 5307421 (1994-04-01), Darboux et al.
patent: 5319564 (1994-06-01), Smayling et al.
patent: 5416729 (1995-05-01), Leon et al.
Beacham et al., "Applications of an Atomic Force Metrology System in Semiconductor Manufacturing", SPIE 1926: 311-321 (1993).
Peters, "AFMs: What Will Their Role Be?", Semiconductor International pp. 62-68, Aug. 1993.
Prolith/2 User's Manual, Finle Technologies, Fourth Edition, Jul. 1993.
Barouch et al., "Modelling Process Latitude in UV Projection Lithography," IEEE Electron Device Letters, vol. 12, No. 10, Oct. 1991, pp. 513-514.
Crisalle et al., "A Comparison of the Optical Projection Lithography Similators in SAMPLE and PROLITH," IEEE Trans. on Semiconductor Manufacturing, vol. 5, No. 1, Feb. 1992, pp. 14-26.
Gopalarao et al., "An Integrated Technology CAD System for Process and Device Designers," IEEE Trans. on VLSI Systems, vol. 1, No. 4, Dec. 1993, pp. 482-490.
Neubauer et al., "Imaging VLSI Cross Sections by Atomic Force Microscopy," 1992 IEEE/IRPS, pp. 299-303.
Rodgers, "Application of the Atomic Force Microscope to Integrated Circuit Reliability and Failure Analysis," 1991 IEEE/IRPS, pp. 250-254.
Qian et al., "A New Scalar Planewave Model for High NA Lithography Simulations," 1994 IEEE/NUPADV, pp. 45-48.
Garbowski Leigh Marie
Teska Kevin J.
VLSI Technology Inc.
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