System and method for verification of a precharge critical path

Details System and method for verification of a precharge critical path System and method for verification of a precharge critical path

1996-07-02

1998-08-25

Voeltz, Emanuel Todd

Boots, shoes, and leggings

G06F 1750

Patent

active

057989389

ABSTRACT:
The present invention provides a system and method for performing precharge timing verification on a logic circuit comprising a plurality of cascaded logic blocks, where in each logic block is implemented via a dynamic logic gate characterized by having a clock resettable output. In addition, a storage element is connected at each input to the logic circuit. The method of the present invention includes the following steps: preconditioning the storage elements so that all the inputs to the logic circuit are driven high when the clock goes high; transitioning the clock high so as to drive all the inputs of the logic circuit high, thereby driving all the outputs of the logic circuit high and discharging the storage node of each logic block; transitioning the clock low to precharge the storage node of all the logic blocks in the logic circuit, and thereby driving all the outputs low; and determining the longest precharge path in the logic circuit. A precharged timing verification system of the present invention is preferably implemented on a computer system and comprises a dynamic simulation mechanism and a precharge timing mechanism for performing the precharge timing verification timing analysis of the present invention.

REFERENCES:
patent: 5051911 (1991-09-01), Kimura
patent: 5095454 (1992-03-01), Huang
patent: 5126950 (1992-06-01), Rees et al.
patent: 5517132 (1996-05-01), Ohara
patent: 5640547 (1997-06-01), Hotta et al.
patent: 5644499 (1997-07-01), Ishii
patent: 5657239 (1997-08-01), Grodstein et al.

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