Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-01-03
2006-01-03
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S019000, C703S021000, C703S022000, C717S124000, C717S127000, C717S129000, C717S135000
Reexamination Certificate
active
06983234
ABSTRACT:
A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high level simulator of the processor. Next, a plurality of checkpoints are established. Then, state data at each of the checkpoints is saved. Finally, the program is run on a plurality of low level simulators of the processor in parallel, where each of the low level simulators is started at a corresponding checkpoint with corresponding state data associated with the corresponding checkpoint.
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Lauterbach, “Accelerating Architectural Simulation by Parallel Execution of Trace Samples”, Tech. Report SMLI TR-93-22, Sun Microsystems Laboratories, Inc., Dec. 1993, pp. 1-14.
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Hangal et al., “Performance Analysis And Validation of the Pico Java Processor,”IEEE Micropp 66-72 (1999).
Hangal Sudheendra
O'Connor James M.
Day Herng-der
Phan Thai
Townsend and Townsend / and Crew LLP
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