System and method for using a DLL for signal timing control...

Details System and method for using a DLL for signal timing control... System and method for using a DLL for signal timing control...

2007-04-14

2009-08-18

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S191000

Reexamination Certificate

active

07577056

ABSTRACT:
The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined delay from the clock signal, and at least one DRAM array coupled to the plurality of control signals, wherein the DRAM array operates in a plurality of steps controlled by the plurality of control signals.

REFERENCES:
patent: 2002/0097626 (2002-07-01), Hidaka
patent: 2002/0141280 (2002-10-01), Hamamoto et al.
patent: 2002/0181297 (2002-12-01), Jones et al.
patent: 2003/0011414 (2003-01-01), Bell
patent: 2007/0133338 (2007-06-01), Hoffmann

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