Electrical computers and digital processing systems: processing – Byte-word rearranging – bit-field insertion or extraction,...
Reexamination Certificate
2000-04-07
2003-09-30
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Byte-word rearranging, bit-field insertion or extraction,...
C712S224000, C708S209000
Reexamination Certificate
active
06629239
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of digital computers and more specifically to functional units for processing predetermined types of instructions. The invention particularly provides a circuit or functional unit for use in connection with execution of an instruction for rearranging bits of a data word in accordance with a mask.
BACKGROUND OF THE INVENTION
Computers process data in accordance with instructions. One type of instruction which has been proposed is a so-called “mingle” instruction which accepts as operands a data word and a mask word and rearranges the bits of the data word in accordance with the mask word. In the rearranged data word, the bits of the data word in bit positions towards the left end of the data word are distributed to bit positions which correspond to bit positions of the mask whose bits are clear, or have the value “zero,” and the bits of the data word in bit positions to the right end of the data word are distributed to bit positions which correspond to bit positions of the mask whose bits are set, while maintaining order of the bits of the data word in each group. For example, if an eight bit data word has the value “abcdefgh” (where the letters represent binary integers having the value “one” or “zero”), and the mask word corresponds to “10011011,” in the rearranged data word generated when the “mingle instruction is executed with these as operands, since three of the eight mask bits are clear the leftmost three bits “a,” “b” and “c” of the data word will be distributed to the bit positions of the mask word which are clear, and since five of the mask bits are set the rightmost bits “d” through “h” will be distributed to the bit positions of the mask word which are set, preserving order in each group, providing output “dabefcgh.”
In a variant of the “mingle” instruction, the bits of the rearranged data word in bit positions for which the bits of the mask are either set or clear (but preferably not both) will be set to a predetermined value. Generally, it has been proposed that, for example, the bits of the rearranged data word in bit positions for which the bits of the mask are clear will be set to zero, but the variant may be used with either group, and the predetermined value may be either “one” or “zero.”
A “mingle” instruction can find utility in connection with, for example, performing various bit permutations, for example, using a mask consisting of alternating set and clear bits will result in a so-called “shuffle” permutation of a data word.
SUMMARY OF THE INVENTION
The invention provides a new and improved circuit or functional unit for use in connection with execution of an instruction for rearranging bits of a data word in accordance with a mask.
In brief summary, the invention provides a system for rearranging an input data word in relation to a mask word, the data word comprising a plurality of input data units in a series of input data unit positions, each associated with a respective one of a plurality of bits of the mask word in a series of mask bit positions, each mask bit having one of a plurality of conditions, to provide an output data word comprising a plurality of output data units in a series of output data unit positions. The system comprises a control module and a shift module. The control module is configured to identify, for each output data unit position, the number of bits in bit positions in the mask word to one end of that bit position which have one of the conditions, and the number of bits in bit positions to another end of the mask word have another of the conditions. The shift module is configured to shift the input data units from their respective input data unit positions each of the bit positions into the respective output data unit positions in response to the identifications generated by the control module and the conditions of the respective mask bits.
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Hillis, W. Daniel & Steele, Guy L. Data Parallel Algorithms,Communications of the ACM, Dec. 1986, vol. 29, No. 12, pp. 1170-1183.
Cesari and McKenna LLP
Sun Microsystems Inc.
Tsai Henry W. H.
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