System and method for transmission rate control in a segmentatio

Details System and method for transmission rate control in a segmentatio System and method for transmission rate control in a segmentatio

1995-08-28

1998-08-18

Chin, Wellington

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370474, 371 55, 3952002, 39520013, H04L 1228, H04L 1256

Patent

active

057967350

ABSTRACT:
A segmentation and reassembly circuit under the ATM standard uses a transmit cell schedule table (TCST) to support real time transmission of ATM cells in multiple constant bit rate virtual channels. In one embodiment, null cells are intentionally scheduled in a TCST. Transmission of the scheduled null cells ("forced null cells") or non-time critical cells are skipped to compensate for delays in an ATM cell transmission schedule, e.g. delays due to a bus latency. During such latency, null cells are generated from a null cell generator and a negative credit counter is incremented for each ATM cell transmission time missed. When transmission of a forced null cell is skipped, the negative credit counter is decremented.

REFERENCES:
patent: 5414702 (1995-05-01), Kudoh
patent: 5602853 (1997-02-01), Ben-Michael et al.
patent: 5625625 (1997-04-01), Oskouy et al.
IDT77201 "155 Mbps ATM SAR Controller for PCI-based Networking Applications" Data Sheet, Integrated Device Technology, Inc, 1996.
Bt8230 "ATM Segmentation and Reassembly Controller--ATM SAR" Data Sheet, Brooktree Corp., Mar. 1995.

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