Electrical computers and digital processing systems: multicomput – Master/slave computer controlling
Reexamination Certificate
1994-09-09
2002-03-12
Geckil, Mehmet B. (Department: 2152)
Electrical computers and digital processing systems: multicomput
Master/slave computer controlling
C709S245000
Reexamination Certificate
active
06356938
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention is directed toward data transfer in multi-processor systems, and more particularly, toward a process for significantly increasing the speed at which data may be throughput between processors via a shared memory.
(2) Description of the Prior Art
Multi-processing systems using a central location from which to store and retrieve data, as well as for sending data between processors comprising the system, are becoming increasingly more popular. Such systems allow for the use of a single memory or central storage area which can be accessed by a plurality of stations. Data work products and the like can be transferred between stations in the system without having to physically transfer floppy disks.
Frequently, a central data base or disk drive is used for storing the data of the individual stations. As the systems become increasingly large, the data stored at the central data base or disk drive also becomes increasingly large. At some point in the use of the system, the data base can be filled with so much data that processing data transfer between stations becomes significantly slowed. Data transfer between multi-processors while using a central disk drive has disadvantages. As is well known in computer technology, retrieving data from a disk drive is significantly slower than retrieving data directly from memory. Using a shared memory in place of a shared disk drive has a significant speed advantage over the same.
The downside to using a shared memory to store data is that space is significantly limited as compared to a disk drive. In order to use a central memory efficiently, it is best to remove data stored therein immediately. It is frequently the case, however that all the information stored in memory is not necessarily the information which is desired to be transmitted to a station of the multi-processor system. Therefore, it is beneficial to provide a means or process for communicating to a station of a multi-processor system from another station, exactly where the data desired for transfer is located in memory.
While the prior art discussed below discloses the use of a memory which may be shared by a plurality of stations comprising a multi-processor system, the transmission of data via the central memory in the systems discussed below is not facilitated by the efficient and inventive process disclosed herein, and thereby such data transfers are inherently significantly slower.
U.S. Pat. No. 4,212,057 to Devlin et al. discloses a shared memory multi/micro processor computer system. The system includes two or more substantially independent processors each having its own bus-type interconnection structure. A shared memory is accessible by any of the processors without interfering with the proper operation of another of the processors. Access to the shared memory is controlled such that a processor is connected to the shared memory only when one request is present. When more than one request is received from the processors, the last processor having received access is given priority to access the shared memory. While a shared memory is used in Devlin et al., there exists no means for improving the efficiency of removing data from the shared memory. That is, the Devlin et al. system fails to provide a means for quick access to the data being transferred, thereby decreasing the efficiency with which the system could perform.
U.S. Pat. No. 4,410,944 to Kronies discloses an apparatus and method for maintaining cache memory integrity in a shared memory environment. Kronies discloses a data processing system having a plurality of processors and a plurality of dedicated and shared memory stations. Each processor includes its own cache for speeding up data transfers between the processor and the shared memory. The integrity of the data in each individual cache, with respect to data written on similar addresses in the shared memory, is maintained by providing the shared memory with a cache monitoring and control system. The system monitors the read and write requests of the processors and in response, maintains an accurate and updatable record of the data addresses used in each individual cache for preventing the same addresses from being overridden, and thereby protecting the integrity of the data. High speed exchange of data from a first processor to a second processor is not disclosed in the Kronies patent. In fact, in Kronies, the data in the shared memory must be scanned before reading and writing requests can be fulfilled, thereby slowing the process by which data is transferred. For such applications, it would be beneficial to facilitate communication between processors prior to the transference of the data. As such, the possibility of threatening the integrity of the data stored could be prevented while increasing throughout instead of delaying it.
U.S. Pat. No. 4,975,833 to Jinzaki discloses a multi-processor system which only allows alternate access to shared memories upon the reception of read and write request signals. The system incorporates lock-out and access flags and a control circuit for controlling access to shared local memories of a group of processors. The lock-out flag inhibits reading from the memory of another processor while the other processor is writing into the memory. The access flag permits reading of the memory by the other processor and inhibits a related processor from writing into the memory while access is given. The Jinzaki system is directed towards sharing local memories and does not incorporate a central memory. The Jinzaki system includes a process for preventing access to data after storage, via communication between processors after storage, thereby slowing data throughput.
U.S. Pat. No. 4,803,618 to Ita et al., discloses a multi processor system having a common memory. The system includes a plurality of processors which use a common memory under a time division control plan. With this system, the common memory is protected from erasure of data stored therein via use of write permission flags given from a master processor. A control unit is operative to receive a write request flag from a processor as well as a write permission flag from the master processor. If both flags are generated simultaneously, the control unit provides a write enable signal for activating the common memory and allowing access thereto. An additional control unit is provided for staggering access to the common memory upon request from a plurality of processors. The Ita et al. system, therefore, provides a means for denying access to a central memory after data has been stored therein, which slows data throughput.
There exists a need in the multi-processor system art for a high speed data transfer process which allows a plurality of processors to prepare for acquiring access of data, prior to its transference to a central memory, so as to provide an efficient data transfer system.
SUMMARY OF THE INVENTION
The primary object of this invention is to provide a system and process for significantly increasing the efficiency of data transfer within multi-processor systems.
Another object of this invention is to provide a process and system for increasing the rate of data transfer between at least two computers of a multi-processor systems which can be implemented with currently available interfacing hardware.
Yet another object of this invention is to provide a high speed data transfer process for use between at least two computers of a multi-processor system using a shared memory.
The foregoing objects are attained by the inventive mapped memory interface process and computer program product of the present invention which process includes providing a provider computer and a consumer computer, each having a local memory and each linked to a shared memory; selecting data stored in the local memory of the provider computer for transfer from the local memory of the provider computer to the shared memory; mapping a portion of the shared memory having a known address for the storage of data; communicating
Bernecky W. Robert
Munoz Jose L.
Geckil Mehmet B.
Lall Prithvi C.
McGowan Michael J.
Oglo Michael F.
The United States of America as represented by the Secretary of
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