Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-03-12
2004-02-10
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395200, C370S395600, C370S469000
Reexamination Certificate
active
06690670
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of communications and computing systems and methods for transmitting and exchanging electronic data between two points, and more specifically, to the field of asynchronous transfer mode in data communications for transporting information across a serial bus.
BACKGROUND OF THE INVENTION
Asynchronous Transfer Mode (ATM) is a protocol-independent, cell-switching network technology that offers high speed and low latency for the support of data, voice, and video and frame relay traffic in real time. ATM provides for the automatic and guaranteed assignment of bandwidth to meet the specific needs of applications, making it ideally suited to support multimedia. ATM also lends itself to upward and downward scaling, making it equally suited for interconnecting local area networks and building wide area networks. ATM based networks may be accessed through a variety of standard interfaces, including frame relay. Although this technology has traditionally been used in local area networks involving workstations and personal computers, it has now been adopted by telephone companies.
ATM is defined in the broadband ISDN protocol at the levels corresponding to levels 1 and 2 of the ISO/OSI model, which are the physical layer and data-link layer. In computer networks, the physical layer is responsible for handling both the mechanical and electrical details of the physical transmission of a bit stream. At the physical layer, the communicating systems agree on the electrical representation of a binary 0 and 1, so that when data are sent as a stream of electrical signals, the receiver is able to interpret the data properly as binary data. This layer is implemented in the hardware of the networking device. The data-link layer is responsible for handling the frames, or fixed-length parts of packets, including any error detection and recovery that occurs in the physical layer.
Voice, video, and data traffic usually are comprised of bytes, packets, or frames. When the traffic reaches an ATM switch, it is segmented into small, fixed-length units called cells. The size of ATM cells is fixed at 53 octets; the cell consists of a 5-octet header and 48-octet payload. The cell header contains the information needed to route the information field through the ATM network.
ATM uses a layered protocol model. ATM has only three layers: the Physical (PHY) layer, the ATM layer and the ATM Adaptation (AAL) layer. The ATM Physical layer currently defines several transport systems, including the Synchronous Optical Network (SONET), T
3
, optical fiber and twisted pair. There are also ATM physical layer definitions for T
1
, E
1
, ADSL, as well as fractional-T
1
(i.e., N×64 Kbps) interfaces. SONET provides the primary transmission infrastructure for implementing public ATM networks, offering service at OC-1 (51.84 Mbps) to OC-12 (622.08 Mbps). Current definitions of SONET go up to OC 192 (9.952 GBps). SONET facilities have only limited availability to many users, however. Therefore, the user-to-network interface (UNI) outlines the use of DS
3
and a PHY layer definition similar to Fiber Distributed Data Interface (FDDI) to provide a 100 Mbps private ATM network interface. The ATM layer provides segmentation and reassembly operations for data services that may use protocol data units (PDUs) different from those of an ATM cell. This layer then is responsible for relaying and routing, as well as multiplexing, the traffic through an ATM network. The AAL resides between the ATM layer and the higher layer protocols and provides the necessary services that are not part of the ATM layer, in order to support the higher-layer protocols.
ATM networks consist of ATM switching systems interconnected by ATM transmission facilities. An ATM switching system is a network element consisting of several physical interfaces, which are tied together via a high speed ATM switching fabric. ATM switching systems perform the function of receiving ATM cell streams on its interfaces, and independently routing each cell to a pre-defined output interface based on its input port, ATM cell header, and associated connection. Cells are routed through the ATM switching system (and network) along a fixed path through the network based on a specified connection and the connection policy attributes. Policy attributes establish certain criteria for the connection which become significant during periods of congestion. ATM switching systems employ buffering and scheduling techniques to minimize traffic loss and ensure connections are properly serviced based on policy attributes during periods of congestion.
Since traffic through an ATM network is asynchronous, it is very possible that cells arriving from a number of different physical interfaces at the same time are all directed to the same physical egress port. The event of scheduling cells from one or more input ports whose combined input rates exceeds the intended link's output rate, results in link congestion. ATM switching systems employ buffering to absorb traffic bursts.
A typical ATM switching system architecture has multiple physical interfaces interconnected via a high speed switching fabric. A typical switch can range in capacity from (16-160) 155 Mbps interfaces and in traffic capacity of 2.5 Gbps to 25+Gbps. ATM layer devices are typically designed to operate at either 155 Mbps or 622 Mbps. The ATM UTOPIA interface partitions the ATM switching system into a PHY layer and ATM layer. The ATM layer is typically associated with the high speed ATM switching fabric. The PHY layer is associated with the physical interface. The PHY layer typically transfers asynchronous cell streams from the ATM layer and adapts them onto the physical transmission medium. The ATM layer and its interface to the switching fabric typically operates at much higher transfer rates than the PHY layer. With the PHY layer having minimal buffering (2-4 cells), and the significant rate mismatch between the PHY and ATM layers, requires an asynchronous transfer control handshake between the ATM/PHY layers of the switch. Consequently the ATM layer typically performs the required cell buffering, traffic scheduling, and congestion control.
The UTOPIA protocol defines a standard interface between the ATM and PHY layers of an ATM switching system. This interface standard allows ATM switch fabrics supplied by 1 device manufacturer to interoperate with PHY devices from another manufacturer. This provides multiple technology supplier alternatives to ATM switch manufacturers. Aside from the UTOPIA standard, there are really no other “standard” interfaces between components in an ATM switching system. For the majority of ATM switching systems, the switch fabric portion of the design is a highly proprietary multi-device switching architecture from a single device supplier.
Since ATM switching fabrics are architected and structured to provide the interconnection of a large number of high bandwidth links, the ATM layer devices are typically designed to support 155 Mbps and now more commonly 622 Mbps interfaces and data rates. The ATM layer devices are fairly costly due to their bandwidth performance, traffic processing complexity, and ability to support large amounts of high-speed cell buffers. They typically have UTOPIA interfaces operating at 25 Mhz or 50 Mhz. What's worse, the 50 Mhz MPHY UTOPIA timing specifications have little to no timing margin, limiting the UTOPIA bus to operation on a single PCB (printed circuit board) or circuit pack within the system. This requires the ATM layer device and its associated PHY's to reside on the same board. This physical restriction really limits the ATM layer's ability to be shared across the maximum number of PHY devices in a system.
For example, a 622 Mbps ATM layer device can support over 300 2.048 Mbps E
1
PHY interfaces. The real-estate requirements for 300 E
1
interfaces is likely to be a factor of 10 higher than would practically fit on a single PCB in a system. In fact, a single 622 Mbps ATM-l
Kizou Hassan
Paradyne Corporation
Thomas Kayden Horstemeyer & Risley LLP
Tsegaye Saba
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