Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
1999-09-22
2001-07-17
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S204000
Reexamination Certificate
active
06263423
ABSTRACT:
The following are commonly owned, co-pending applications:
“A ROM With RAM Cell and Cyclic Redundancy Check Circuit”, application Ser. No. 07/802,816, filed Dec. 6, 1992, now abandoned;
“High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution”, application Ser. No. 07/817,810, filed Jan. 8, 1992 now U.S. Pat. No. 5,539,911;
“High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution”, Ser. No. 08/397,016 filed Mar. 1, 1995, now U.S. Pat. No. 5,560,032, which is a file wrapper continuation of application Ser. No. 07/817,809, filed Jan. 8, 1992.
The disclosures of the above applications are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the invention generally relates to superscalar RISC microprocessors, more specifically, the invention relates to a CISC to RISC microprocessor instruction alignment unit and decode unit for permitting complex instructions to run on RISC-based hardware.
2. Related Art
All complex instruction set computers (CISC computers) which use variable length instructions are faced with the problem of determining the length of each instruction that is encountered in the instruction stream. Instructions are packed into memory as successive bytes of data, so that given the address of an instruction, it is possible to determine the starting address of the next instruction if you know the first instruction's length.
For a conventional processor, this length determination does not have a significant performance impact compared to other stages in the processing of an instruction stream, such as the actual execution of each instruction. As a result, fairly simple circuits are typically used. Superscalar reduced instruction set computers (RISC computers), on the other hand, can process instructions at a much higher rate, requiring instructions to be extracted from memory much more rapidly to keep up with the parallel execution of multiple instructions. This limiting factor imposed by the rate at which instructions can be extracted from memory is referred to as the Flynn Bottleneck.
The task of determining the length of each instruction and extracting that instruction from the instruction stream is performed by a function unit called an Instruction Align Unit (IAU). This block must contain decoder logic to determine the instruction length, and a shifter to align the instruction data with the decoder logic.
For the Intel 80386 microprocessor, the first byte of an instruction can have numerous implications on the overall instruction length, and may require that additional bytes be checked before the final length is known. Furthermore, the additional bytes may specify other additional bytes. It is therefore extremely difficult to quickly determine the length of the X86 instruction because the process is inherently sequential.
Based on the information provided in the i486™ Programmer's Reference Guide, several conclusions can be drawn regarding alignment unit present in the i486™. The i486™'s IAU is designed to look only at the first few bytes of the instruction. In cases where these bytes do not fully specify the length, these initial bytes are extracted and the process is repeated on the remaining bytes. Each iteration of this process requires a full cycle, so it may take several cycles, at worst case, for an instruction to be fully aligned.
Situations that require additional cycles for the i486™ IAU include the presence of prefixed and escaped (2 byte) opcodes. Both of these are common in i486™ programs. In addition, complex instructions may also comprise displacement and immediate data. The i486™ requires additional time to extract this data.
An example format for a CISC processor instruction is shown in FIG.
1
. The example depicts the potential bytes of a variable length i486™ CISC instruction. The instructions are stored in memory on byte boundaries. The minimum length of an instruction is 1 byte, and the maximum length of an instruction, including prefixes, is 15 bytes. The total length of the instruction is determined by the Prefixes Opcode, ModR/M and SIB bytes.
SUMMARY OF THE INVENTION
The present invention is a subsystem and method of a microprocessor having a superscalar reduced instruction set computer (RISC) processor designed to emulate a complex instruction set computer (CISC), such as an Intel 80×86 microprocessor, or other CISC processors.
The CISC to RISC translation operation of the present invention involves two basic steps. CISC instructions must first be extracted from the instruction stream, and then decoded to generate nano-instructions that can be processed by the RISC processor. These steps are performed by an Instruction Alignment Unit (IAU) and an Instruction Decode Unit (IDU), respectively.
The IAU functions to extract individual CISC instructions from the instruction stream by looking at the oldest 23 bytes on instruction data. The IAU extracts 8 continuous bytes starting with any byte in a bottom line of an Instruction FIFO. During each clock phase, the IAU determines the length of the current instruction and uses this information to control two shifters to shift out the current instruction, leaving the next sequential instruction in the stream. The IAU therefore outputs an aligned instruction during each clock phase, for a peak rate of two instructions per cycle. Exceptions to this best case performance are discussed below in sections 2.0 and 2.1.
After CISC instructions have been extracted from memory, the IDU functions to convert these aligned instructions to equivalent sequences of RISC instructions, called nano-instructions. The IDU looks at each aligned instruction as it is output by the IAU, and decodes it to determine various factors such as the number and type of nano-instruction(s) required, the size of the data operands, and whether or not a memory access is required to complete the aligned instruction. Simple instructions are directly translated by decoder hardware into nano-instructions, while more complex CISC instructions are emulated by subroutines in a special instruction set, called microcode routines, which are then decoded into nano-instructions. This information is collected for two instructions during a complete cycle, and then combined together to form an instruction bucket, containing the nano-instructions corresponding to both source instructions. This bucket is then transferred to an Instructions Execution Unit (IEU) for execution by a RISC processor. The execution of the nano-instruction buckets is outside the scope of the present invention.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
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Coon Brett
Miyayama Yoshiyuki
Nguyen Le Trong
Wang Johannes
An Meng-Al T.
Chang Jung-won
Seiko Epson Corporation
Sterne Kessler Goldstein & Fox P.L.L.C.
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