Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-21
2003-05-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185080, C365S185110
Reexamination Certificate
active
06563739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory controller and in particular to a memory controller for controlling the transmission of data to and from a memory array comprising at least a first type and a second type of memory.
2. Description of the Prior Art
An example of a known memory controller is described in U.S. Pat. No. 5,721,860.
SUMMARY OF THE INVENTION
In accordance with the invention there is provided a memory controller for controlling the transfer of data to and from a memory array, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the memory controller comprises:
an address decoder having an input for receiving a memory access request, said memory access request including the address of the memory array to be accessed, and an output for outputting the address of the memory array to be accessed;
a first sub-controller for generating a plurality of memory interface signals for controlling the first type of memory, said first sub-controller being operated in response to addresses within a first range of addresses output by the address decoder; and
a second sub-controller for generating a plurality of memory interface signals for controlling the second type of memory, said second sub-controller being operated in response to addresses within a second, non-overlapping range of addresses output by the address decoder.
A user can therefore define the areas of memory to be dedicated to a particular type of memory and add these types of memory as and when required. Such a memory controller therefore provides a user with the flexibility to connect different types of memory to a device via a single bus and to store information as to the address range to be allocated to a particular type of memory.
The memory controller of the invention may be used in a variety of electronic devices such as portable radio telecommunications devices (e.g. telephones and communicators).
Preferably the first type of memory is a burst mode type of memory, in particular flash memory. The memory may be synchronous or asynchronous. The addressing protocol may include multiplexed address and data.
Preferably parameters of the memory controller are configurable e.g. the first and second range of addresses may be configurable.
In accordance with the invention there is also provided a method of controlling the transfer of data to and from a memory array in an electronic device, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the method comprises:
receiving a memory access request, said memory access request including the address of the memory array to be accessed, and outputting the address of the memory array to be accessed;
in response to addresses within a first range of addresses generating a plurality of memory interface signals for controlling the first type of memory; and
in response to addresses within a second, non-overlapping range of addresses generating a plurality of memory interface signals for controlling the second type of memory.
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Aho Ari
Floman Matti
Lipponen Markku
Antonelli Terry Stout & Kraus LLP
Auduong Gene N.
Nelms David
Nokia Mobile Phones Limited
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