Television – Image signal processing circuitry specific to television – With details of static storage device
Reexamination Certificate
1997-10-02
2002-08-20
Kostak, Victor R. (Department: 2711)
Television
Image signal processing circuitry specific to television
With details of static storage device
C348S716000, C348S448000
Reexamination Certificate
active
06437835
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to display of video for displaying a video signal such as interlaced video, e.g. a television video signal or a video signal obtained from a laser disk, on a non-interlacing display device of an information processing apparatus. More particularly, the invention relates to display of video data on the display device of a system via a system bus.
1. Background of the Invention
The format for displaying video from a television or laser disk is an interlaced display format in which even-numbered scanning lines and odd-numbered scanning lines are alternately displayed every {fraction (1/60)} of a second. The even-numbered scanning lines are referred to collectively as an even field and the odd-numbered scanning line are referred to collectively as an odd field. An even field and an odd field are combined to form a frame.
In an information processing apparatus such as a personal computer, there are instances where an interlaced video signal (from a television or laser disk) is acquired and displayed on a non-interlacing display device. In such cases, a so-called overlay technique is required. Several methods are used to achieve overlay.
According to one method, which is an independent path scheme, as shown in
FIG. 5
, a video display path which includes a video input unit
54
, a video display device
55
and a buffer
56
is provided separately of a system display path which includes a system bus
51
, a system display device
52
and a buffer
53
. Overlay is achieved by changing over a display changeover switch
57
at the final display stage.
According to a second method, which is illustrated in
FIG. 6
, video data from a video input
64
flows into a buffer
63
of a system display device
62
via a system bus
61
so that overlay is implemented solely by the system display path.
2. Discussion of the Related Art
Towards the present invention the following problems have been encountered according to the inventor's analysis.
In the first method described above, the video display path and the system display path are independent of each other even though overlay is achieved. Consequently, though there is no influence upon the performance of the overall system, a problem which arises is that it is difficult to control the timing of the switch
57
at the final display stage.
By contrast, the second method dispenses with switch control at the final display stage and the circuit arrangement is simpler than that of the first method. However, since the video data is displayed via the system bus, the influence upon the performance of the overall system is great.
In the system of the second method, the video data must be transferred to the system bus periodically. In addition, it is required that a fixed amount of data be transferred at all times. In a case where utilization of the system bus cannot be acquired periodically, frames go missing from the video picture and smooth motion cannot be achieved.
Further, the system bus used in modern personal computers is such that when one of a number of devices connected to the system bus is utilizing the bus, the other devices cannot utilize the bus. Consequently, when the system bus is occupied periodically in order to display video, a decline in the performance of the system is unavoidable.
In a display of video data, the field data must be updated on the average of every {fraction (1/60)} of a second. The reason for the update on the average of every {fraction (1/60)} of a second is that there are cases where the picture update frequency on the system display side differs from the picture update frequency of the video signal. Accordingly, it is required that the system bus be acquired periodically every {fraction (1/60)} of a second.
Further, with regard to video data, data transfer at a rate of e.g. 20 megabytes per second must be carried out at all times.
A PCI (Peripheral Component Interface) bus, for example, is used as the general system bus in modern personal computers. The data transfer capability of this bus is a maximum of 132 megabytes per second. However, in the ordinary operating state, the data transfer capability is at most 50 to 60 percent of the maximum value, depending upon the load connected to the system bus.
Further, LSI chips of this kind currently available do not perform the buffer control carried out by special-purpose LSI chips or the like for processing video signals. This means that the buffer on the system display side must be written in sync with the input timing of the video data.
By way of example, refer to “Multimedia bridge scaler and PCI circuit” in the Philips Semiconductors publication DATA HANDBOOK IC22, July 1995, pp. 653~654.
In general, the system display side is not equipped with a function for presenting a field display with respect to a video input signal of this kind, and for this reason a frame display is presented. This gives rise to a phenomenon, referred to as a “motion artifact”, in which contour lines produced by motion resulting from the time difference between interlaced fields take on jagged appearance.
Further, in the conventional systems, no consideration is given to means for reducing the amount of data transfer.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a video display scheme, system, or method in which the occupancy of a system bus at the time of a video data transfer is reduced and/or the occurrence of motion artifacts in a frame display is avoided.
It is another object of the present invention to provide a computer system which allows a video display receiving an interlaced video signal but can display the same in the non-interlaced video displaying system with a reduced occupancy of a system bus. Further objects of the present invention will become apparent in the entire disclosure.
According to the present invention, there is provided a video display system for storing interlaced video data in a buffer of a non-interlacing image display device via a system bus and displaying the video data, wherein the video display system has a frame buffer and only a difference from an immediately preceding picture is transferred to the system bus.
More specifically, according to the gist of the present invention, new frame information is created by interpolating entered interlaced video data based on a difference between fields and immediately preceding display frame information, transferring only the difference from the immediately preceding display frame information to the system bus and presenting a frame display.
In accordance with the present invention thus constructed, motion artifacts are not displayed and occupancy of the system bus is reduced.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.
REFERENCES:
patent: 4969042 (1990-11-01), Houtman
patent: 5301240 (1994-04-01), Stockum et al.
patent: 5682208 (1997-10-01), Harney
patent: 5835636 (1998-11-01), Auld
Phillips Semiconductor Data Handbook, May 1995, “Multimedia bridge scaler and PCI circuit”.
Kostak Victor R.
Michael Best & Friedrich Laff, Whitesel & Saret, Ltd., LLC
NEC Corporation
Whitesel, Ltd. J. Warren
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