System and method for tolerating dynamic circuit decay

Details System and method for tolerating dynamic circuit decay System and method for tolerating dynamic circuit decay

1992-05-19

1994-08-30

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307268, H03K 19003

Patent

active

053430964

ABSTRACT:
The present invention tolerates the decay of a dynamic logic circuit by preserving the logic state of the output before the decay. A slow clock detector is configured to detect a slow clock condition of the clock pertaining to the dynamic logic circuit. A tolerant storage device is configured to preserve the data output by command of the slow clock detector upon a detection of the slow clock condition.

REFERENCES:
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4614973 (1986-09-01), Sorenson
patent: 4686386 (1987-08-01), Tadao
patent: 5004933 (1991-04-01), Widener
patent: 5086236 (1992-02-01), Feemster
patent: 5087835 (1992-02-01), Hattangadi
patent: 5155393 (1992-10-01), Gongwen et al.

Affiliated with

Also associated with

Rating

System and method for tolerating dynamic circuit decay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for tolerating dynamic circuit decay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for tolerating dynamic circuit decay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-31598