System and method for testing the operation of a DLL-based...

Details System and method for testing the operation of a DLL-based... System and method for testing the operation of a DLL-based...

2007-10-30

2007-10-30

Pham, Chi (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S535000, C370S537000, C375S371000

Reexamination Certificate

active

10778419

ABSTRACT:
A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

REFERENCES:
patent: 7082546 (2006-07-01), Schoch

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